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Merge tag 'phy-fixes-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy fixes from Vinod Koul: - Qualcomm QMP X1E80100 PCIe Gen4 PHY initialisation fix - Freescale imx8mq tuning parameter name fix - Samsung exynos5 fir for error code in probe() - Xilinx Zynqmp SGMII linkup failure fix * tag 'phy-fixes-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: xilinx: phy-zynqmp: Fix SGMII linkup failure on resume phy: exynos5-usbdrd: fix error code in probe() phy: fsl-imx8mq-usb: fix tuning parameter name phy: qcom: qmp-pcie: Fix X1E80100 PCIe Gen4 PHY initialisation
2 parents 8d80c99 + 5af9b30 commit 32fafaf

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+74
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lines changed

‎drivers/phy/freescale/phy-fsl-imx8mq-usb.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ static void imx8m_get_phy_tuning_data(struct imx8mq_usb_phy *imx_phy)
176176
imx_phy->comp_dis_tune =
177177
phy_comp_dis_tune_from_property(imx_phy->comp_dis_tune);
178178

179-
if (device_property_read_u32(dev, "fsl,pcs-tx-deemph-3p5db-attenuation-db",
179+
if (device_property_read_u32(dev, "fsl,phy-pcs-tx-deemph-3p5db-attenuation-db",
180180
&imx_phy->pcs_tx_deemph_3p5db))
181181
imx_phy->pcs_tx_deemph_3p5db = PHY_TUNE_DEFAULT;
182182
else

‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1245,8 +1245,8 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = {
12451245
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
12461246
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
12471247
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1248-
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1249-
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1248+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
1249+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
12501250
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),
12511251
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
12521252
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
@@ -1263,6 +1263,7 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
12631263
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
12641264
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
12651265
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1266+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
12661267
};
12671268

12681269
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {
@@ -1286,12 +1287,15 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = {
12861287
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),
12871288
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),
12881289
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1289-
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b),
1290+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1),
1291+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2),
1292+
QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
12901293
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
12911294
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
12921295
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
12931296
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1294-
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1297+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1),
1298+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2),
12951299
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
12961300
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
12971301
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
@@ -1307,13 +1311,16 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = {
13071311
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),
13081312
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
13091313
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1314+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
13101315
};
13111316

13121317
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {
13131318
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
13141319
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
13151320
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
13161321
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1322+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
1323+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
13171324
};
13181325

13191326
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
@@ -1324,11 +1331,13 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
13241331
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
13251332
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
13261333
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1334+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
1335+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
13271336
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
13281337
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1329-
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
1330-
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
1331-
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
1338+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18),
1339+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
1340+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
13321341
};
13331342

13341343
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {

‎drivers/phy/samsung/phy-exynos5-usbdrd.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1745,7 +1745,7 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
17451745
sizeof(*phy_drd->regulators),
17461746
GFP_KERNEL);
17471747
if (!phy_drd->regulators)
1748-
return ENOMEM;
1748+
return -ENOMEM;
17491749
regulator_bulk_set_supply_names(phy_drd->regulators,
17501750
drv_data->regulator_names,
17511751
drv_data->n_regulators);

‎drivers/phy/xilinx/phy-zynqmp.c‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -160,6 +160,24 @@ static const char *const xpsgtr_icm_str[] = {
160160
/* Timeout values */
161161
#define TIMEOUT_US 1000
162162

163+
/* Lane 0/1/2/3 offset */
164+
#define DIG_8(n) ((0x4000 * (n)) + 0x1074)
165+
#define ILL13(n) ((0x4000 * (n)) + 0x1994)
166+
#define DIG_10(n) ((0x4000 * (n)) + 0x107c)
167+
#define RST_DLY(n) ((0x4000 * (n)) + 0x19a4)
168+
#define BYP_15(n) ((0x4000 * (n)) + 0x1038)
169+
#define BYP_12(n) ((0x4000 * (n)) + 0x102c)
170+
#define MISC3(n) ((0x4000 * (n)) + 0x19ac)
171+
#define EQ11(n) ((0x4000 * (n)) + 0x1978)
172+
173+
static u32 save_reg_address[] = {
174+
/* Lane 0/1/2/3 Register */
175+
DIG_8(0), ILL13(0), DIG_10(0), RST_DLY(0), BYP_15(0), BYP_12(0), MISC3(0), EQ11(0),
176+
DIG_8(1), ILL13(1), DIG_10(1), RST_DLY(1), BYP_15(1), BYP_12(1), MISC3(1), EQ11(1),
177+
DIG_8(2), ILL13(2), DIG_10(2), RST_DLY(2), BYP_15(2), BYP_12(2), MISC3(2), EQ11(2),
178+
DIG_8(3), ILL13(3), DIG_10(3), RST_DLY(3), BYP_15(3), BYP_12(3), MISC3(3), EQ11(3),
179+
};
180+
163181
struct xpsgtr_dev;
164182

165183
/**
@@ -209,6 +227,7 @@ struct xpsgtr_phy {
209227
* @tx_term_fix: fix for GT issue
210228
* @saved_icm_cfg0: stored value of ICM CFG0 register
211229
* @saved_icm_cfg1: stored value of ICM CFG1 register
230+
* @saved_regs: registers to be saved/restored during suspend/resume
212231
*/
213232
struct xpsgtr_dev {
214233
struct device *dev;
@@ -221,6 +240,7 @@ struct xpsgtr_dev {
221240
bool tx_term_fix;
222241
unsigned int saved_icm_cfg0;
223242
unsigned int saved_icm_cfg1;
243+
u32 *saved_regs;
224244
};
225245

226246
/*
@@ -294,6 +314,32 @@ static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
294314
writel((readl(addr) & ~clr) | set, addr);
295315
}
296316

317+
/**
318+
* xpsgtr_save_lane_regs - Saves registers on suspend
319+
* @gtr_dev: pointer to phy controller context structure
320+
*/
321+
static void xpsgtr_save_lane_regs(struct xpsgtr_dev *gtr_dev)
322+
{
323+
int i;
324+
325+
for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
326+
gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev,
327+
save_reg_address[i]);
328+
}
329+
330+
/**
331+
* xpsgtr_restore_lane_regs - Restores registers on resume
332+
* @gtr_dev: pointer to phy controller context structure
333+
*/
334+
static void xpsgtr_restore_lane_regs(struct xpsgtr_dev *gtr_dev)
335+
{
336+
int i;
337+
338+
for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
339+
xpsgtr_write(gtr_dev, save_reg_address[i],
340+
gtr_dev->saved_regs[i]);
341+
}
342+
297343
/*
298344
* Hardware Configuration
299345
*/
@@ -837,6 +883,8 @@ static int xpsgtr_runtime_suspend(struct device *dev)
837883
gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
838884
gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
839885

886+
xpsgtr_save_lane_regs(gtr_dev);
887+
840888
return 0;
841889
}
842890

@@ -847,6 +895,8 @@ static int xpsgtr_runtime_resume(struct device *dev)
847895
unsigned int i;
848896
bool skip_phy_init;
849897

898+
xpsgtr_restore_lane_regs(gtr_dev);
899+
850900
icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
851901
icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
852902

@@ -994,6 +1044,12 @@ static int xpsgtr_probe(struct platform_device *pdev)
9941044
return ret;
9951045
}
9961046

1047+
gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev,
1048+
sizeof(save_reg_address),
1049+
GFP_KERNEL);
1050+
if (!gtr_dev->saved_regs)
1051+
return -ENOMEM;
1052+
9971053
return 0;
9981054
}
9991055

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