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KVM: arm64: nv: Describe trap behaviour of MDCR_EL2.HPMN
MDCR_EL2.HPMN splits the PMU event counters into two ranges: the first range is accessible from all ELs, and the second range is accessible only to EL2/3. Supposing the guest hypervisor allows direct access to the PMU counters from the L2, KVM needs to locally handle those accesses. Add a new complex trap configuration for HPMN that checks if the counter index is accessible to the current context. As written, the architecture suggests HPMN only causes PMEVCNTR<n>_EL0 to trap, though intuition (and the pseudocode) suggest that the trap applies to PMEVTYPER<n>_EL0 as well. Reviewed-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Oliver Upton <[email protected]>
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3 files changed

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lines changed

‎arch/arm64/kvm/emulate-nested.c‎

Lines changed: 96 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,7 @@ enum cgt_group_id {
110110
CGT_HCR_TPU_TOCU,
111111
CGT_HCR_NV1_nNV2_ENSCXT,
112112
CGT_MDCR_TPM_TPMCR,
113+
CGT_MDCR_TPM_HPMN,
113114
CGT_MDCR_TDE_TDA,
114115
CGT_MDCR_TDE_TDOSA,
115116
CGT_MDCR_TDE_TDRA,
@@ -126,6 +127,7 @@ enum cgt_group_id {
126127
CGT_CNTHCTL_EL1PTEN,
127128

128129
CGT_CPTR_TTA,
130+
CGT_MDCR_HPMN,
129131

130132
/* Must be last */
131133
__NR_CGT_GROUP_IDS__
@@ -441,6 +443,7 @@ static const enum cgt_group_id *coarse_control_combo[] = {
441443
MCB(CGT_HCR_TPU_TOCU, CGT_HCR_TPU, CGT_HCR_TOCU),
442444
MCB(CGT_HCR_NV1_nNV2_ENSCXT, CGT_HCR_NV1_nNV2, CGT_HCR_ENSCXT),
443445
MCB(CGT_MDCR_TPM_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TPMCR),
446+
MCB(CGT_MDCR_TPM_HPMN, CGT_MDCR_TPM, CGT_MDCR_HPMN),
444447
MCB(CGT_MDCR_TDE_TDA, CGT_MDCR_TDE, CGT_MDCR_TDA),
445448
MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA),
446449
MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA),
@@ -504,13 +507,42 @@ static enum trap_behaviour check_cptr_tta(struct kvm_vcpu *vcpu)
504507
return BEHAVE_HANDLE_LOCALLY;
505508
}
506509

510+
static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu)
511+
{
512+
u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
513+
unsigned int idx;
514+
515+
516+
switch (sysreg) {
517+
case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30):
518+
case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30):
519+
idx = (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg);
520+
break;
521+
case SYS_PMXEVTYPER_EL0:
522+
case SYS_PMXEVCNTR_EL0:
523+
idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
524+
__vcpu_sys_reg(vcpu, PMSELR_EL0));
525+
break;
526+
default:
527+
/* Someone used this trap helper for something else... */
528+
KVM_BUG_ON(1, vcpu->kvm);
529+
return BEHAVE_HANDLE_LOCALLY;
530+
}
531+
532+
if (kvm_pmu_counter_is_hyp(vcpu, idx))
533+
return BEHAVE_FORWARD_RW | BEHAVE_FORWARD_IN_HOST_EL0;
534+
535+
return BEHAVE_HANDLE_LOCALLY;
536+
}
537+
507538
#define CCC(id, fn) \
508539
[id - __COMPLEX_CONDITIONS__] = fn
509540

510541
static const complex_condition_check ccc[] = {
511542
CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten),
512543
CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten),
513544
CCC(CGT_CPTR_TTA, check_cptr_tta),
545+
CCC(CGT_MDCR_HPMN, check_mdcr_hpmn),
514546
};
515547

516548
/*
@@ -925,77 +957,77 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
925957
SR_TRAP(SYS_PMOVSCLR_EL0, CGT_MDCR_TPM),
926958
SR_TRAP(SYS_PMCEID0_EL0, CGT_MDCR_TPM),
927959
SR_TRAP(SYS_PMCEID1_EL0, CGT_MDCR_TPM),
928-
SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM),
960+
SR_TRAP(SYS_PMXEVTYPER_EL0, CGT_MDCR_TPM_HPMN),
929961
SR_TRAP(SYS_PMSWINC_EL0, CGT_MDCR_TPM),
930962
SR_TRAP(SYS_PMSELR_EL0, CGT_MDCR_TPM),
931-
SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM),
963+
SR_TRAP(SYS_PMXEVCNTR_EL0, CGT_MDCR_TPM_HPMN),
932964
SR_TRAP(SYS_PMCCNTR_EL0, CGT_MDCR_TPM),
933965
SR_TRAP(SYS_PMUSERENR_EL0, CGT_MDCR_TPM),
934966
SR_TRAP(SYS_PMINTENSET_EL1, CGT_MDCR_TPM),
935967
SR_TRAP(SYS_PMINTENCLR_EL1, CGT_MDCR_TPM),
936968
SR_TRAP(SYS_PMMIR_EL1, CGT_MDCR_TPM),
937-
SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM),
938-
SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM),
939-
SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM),
940-
SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM),
941-
SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM),
942-
SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM),
943-
SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM),
944-
SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM),
945-
SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM),
946-
SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM),
947-
SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM),
948-
SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM),
949-
SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM),
950-
SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM),
951-
SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM),
952-
SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM),
953-
SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM),
954-
SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM),
955-
SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM),
956-
SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM),
957-
SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM),
958-
SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM),
959-
SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM),
960-
SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM),
961-
SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM),
962-
SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM),
963-
SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM),
964-
SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM),
965-
SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM),
966-
SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM),
967-
SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM),
968-
SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM),
969-
SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM),
970-
SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM),
971-
SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM),
972-
SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM),
973-
SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM),
974-
SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM),
975-
SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM),
976-
SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM),
977-
SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM),
978-
SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM),
979-
SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM),
980-
SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM),
981-
SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM),
982-
SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM),
983-
SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM),
984-
SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM),
985-
SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM),
986-
SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM),
987-
SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM),
988-
SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM),
989-
SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM),
990-
SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM),
991-
SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM),
992-
SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM),
993-
SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM),
994-
SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM),
995-
SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM),
996-
SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM),
997-
SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM),
998-
SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM),
969+
SR_TRAP(SYS_PMEVCNTRn_EL0(0), CGT_MDCR_TPM_HPMN),
970+
SR_TRAP(SYS_PMEVCNTRn_EL0(1), CGT_MDCR_TPM_HPMN),
971+
SR_TRAP(SYS_PMEVCNTRn_EL0(2), CGT_MDCR_TPM_HPMN),
972+
SR_TRAP(SYS_PMEVCNTRn_EL0(3), CGT_MDCR_TPM_HPMN),
973+
SR_TRAP(SYS_PMEVCNTRn_EL0(4), CGT_MDCR_TPM_HPMN),
974+
SR_TRAP(SYS_PMEVCNTRn_EL0(5), CGT_MDCR_TPM_HPMN),
975+
SR_TRAP(SYS_PMEVCNTRn_EL0(6), CGT_MDCR_TPM_HPMN),
976+
SR_TRAP(SYS_PMEVCNTRn_EL0(7), CGT_MDCR_TPM_HPMN),
977+
SR_TRAP(SYS_PMEVCNTRn_EL0(8), CGT_MDCR_TPM_HPMN),
978+
SR_TRAP(SYS_PMEVCNTRn_EL0(9), CGT_MDCR_TPM_HPMN),
979+
SR_TRAP(SYS_PMEVCNTRn_EL0(10), CGT_MDCR_TPM_HPMN),
980+
SR_TRAP(SYS_PMEVCNTRn_EL0(11), CGT_MDCR_TPM_HPMN),
981+
SR_TRAP(SYS_PMEVCNTRn_EL0(12), CGT_MDCR_TPM_HPMN),
982+
SR_TRAP(SYS_PMEVCNTRn_EL0(13), CGT_MDCR_TPM_HPMN),
983+
SR_TRAP(SYS_PMEVCNTRn_EL0(14), CGT_MDCR_TPM_HPMN),
984+
SR_TRAP(SYS_PMEVCNTRn_EL0(15), CGT_MDCR_TPM_HPMN),
985+
SR_TRAP(SYS_PMEVCNTRn_EL0(16), CGT_MDCR_TPM_HPMN),
986+
SR_TRAP(SYS_PMEVCNTRn_EL0(17), CGT_MDCR_TPM_HPMN),
987+
SR_TRAP(SYS_PMEVCNTRn_EL0(18), CGT_MDCR_TPM_HPMN),
988+
SR_TRAP(SYS_PMEVCNTRn_EL0(19), CGT_MDCR_TPM_HPMN),
989+
SR_TRAP(SYS_PMEVCNTRn_EL0(20), CGT_MDCR_TPM_HPMN),
990+
SR_TRAP(SYS_PMEVCNTRn_EL0(21), CGT_MDCR_TPM_HPMN),
991+
SR_TRAP(SYS_PMEVCNTRn_EL0(22), CGT_MDCR_TPM_HPMN),
992+
SR_TRAP(SYS_PMEVCNTRn_EL0(23), CGT_MDCR_TPM_HPMN),
993+
SR_TRAP(SYS_PMEVCNTRn_EL0(24), CGT_MDCR_TPM_HPMN),
994+
SR_TRAP(SYS_PMEVCNTRn_EL0(25), CGT_MDCR_TPM_HPMN),
995+
SR_TRAP(SYS_PMEVCNTRn_EL0(26), CGT_MDCR_TPM_HPMN),
996+
SR_TRAP(SYS_PMEVCNTRn_EL0(27), CGT_MDCR_TPM_HPMN),
997+
SR_TRAP(SYS_PMEVCNTRn_EL0(28), CGT_MDCR_TPM_HPMN),
998+
SR_TRAP(SYS_PMEVCNTRn_EL0(29), CGT_MDCR_TPM_HPMN),
999+
SR_TRAP(SYS_PMEVCNTRn_EL0(30), CGT_MDCR_TPM_HPMN),
1000+
SR_TRAP(SYS_PMEVTYPERn_EL0(0), CGT_MDCR_TPM_HPMN),
1001+
SR_TRAP(SYS_PMEVTYPERn_EL0(1), CGT_MDCR_TPM_HPMN),
1002+
SR_TRAP(SYS_PMEVTYPERn_EL0(2), CGT_MDCR_TPM_HPMN),
1003+
SR_TRAP(SYS_PMEVTYPERn_EL0(3), CGT_MDCR_TPM_HPMN),
1004+
SR_TRAP(SYS_PMEVTYPERn_EL0(4), CGT_MDCR_TPM_HPMN),
1005+
SR_TRAP(SYS_PMEVTYPERn_EL0(5), CGT_MDCR_TPM_HPMN),
1006+
SR_TRAP(SYS_PMEVTYPERn_EL0(6), CGT_MDCR_TPM_HPMN),
1007+
SR_TRAP(SYS_PMEVTYPERn_EL0(7), CGT_MDCR_TPM_HPMN),
1008+
SR_TRAP(SYS_PMEVTYPERn_EL0(8), CGT_MDCR_TPM_HPMN),
1009+
SR_TRAP(SYS_PMEVTYPERn_EL0(9), CGT_MDCR_TPM_HPMN),
1010+
SR_TRAP(SYS_PMEVTYPERn_EL0(10), CGT_MDCR_TPM_HPMN),
1011+
SR_TRAP(SYS_PMEVTYPERn_EL0(11), CGT_MDCR_TPM_HPMN),
1012+
SR_TRAP(SYS_PMEVTYPERn_EL0(12), CGT_MDCR_TPM_HPMN),
1013+
SR_TRAP(SYS_PMEVTYPERn_EL0(13), CGT_MDCR_TPM_HPMN),
1014+
SR_TRAP(SYS_PMEVTYPERn_EL0(14), CGT_MDCR_TPM_HPMN),
1015+
SR_TRAP(SYS_PMEVTYPERn_EL0(15), CGT_MDCR_TPM_HPMN),
1016+
SR_TRAP(SYS_PMEVTYPERn_EL0(16), CGT_MDCR_TPM_HPMN),
1017+
SR_TRAP(SYS_PMEVTYPERn_EL0(17), CGT_MDCR_TPM_HPMN),
1018+
SR_TRAP(SYS_PMEVTYPERn_EL0(18), CGT_MDCR_TPM_HPMN),
1019+
SR_TRAP(SYS_PMEVTYPERn_EL0(19), CGT_MDCR_TPM_HPMN),
1020+
SR_TRAP(SYS_PMEVTYPERn_EL0(20), CGT_MDCR_TPM_HPMN),
1021+
SR_TRAP(SYS_PMEVTYPERn_EL0(21), CGT_MDCR_TPM_HPMN),
1022+
SR_TRAP(SYS_PMEVTYPERn_EL0(22), CGT_MDCR_TPM_HPMN),
1023+
SR_TRAP(SYS_PMEVTYPERn_EL0(23), CGT_MDCR_TPM_HPMN),
1024+
SR_TRAP(SYS_PMEVTYPERn_EL0(24), CGT_MDCR_TPM_HPMN),
1025+
SR_TRAP(SYS_PMEVTYPERn_EL0(25), CGT_MDCR_TPM_HPMN),
1026+
SR_TRAP(SYS_PMEVTYPERn_EL0(26), CGT_MDCR_TPM_HPMN),
1027+
SR_TRAP(SYS_PMEVTYPERn_EL0(27), CGT_MDCR_TPM_HPMN),
1028+
SR_TRAP(SYS_PMEVTYPERn_EL0(28), CGT_MDCR_TPM_HPMN),
1029+
SR_TRAP(SYS_PMEVTYPERn_EL0(29), CGT_MDCR_TPM_HPMN),
1030+
SR_TRAP(SYS_PMEVTYPERn_EL0(30), CGT_MDCR_TPM_HPMN),
9991031
SR_TRAP(SYS_PMCCFILTR_EL0, CGT_MDCR_TPM),
10001032
SR_TRAP(SYS_MDCCSR_EL0, CGT_MDCR_TDCC_TDE_TDA),
10011033
SR_TRAP(SYS_MDCCINT_EL1, CGT_MDCR_TDCC_TDE_TDA),

‎arch/arm64/kvm/pmu-emul.c‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -265,6 +265,24 @@ void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu)
265265
irq_work_sync(&vcpu->arch.pmu.overflow_work);
266266
}
267267

268+
bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx)
269+
{
270+
unsigned int hpmn;
271+
272+
if (!vcpu_has_nv(vcpu) || idx == ARMV8_PMU_CYCLE_IDX)
273+
return false;
274+
275+
/*
276+
* Programming HPMN=0 is CONSTRAINED UNPREDICTABLE if FEAT_HPMN0 isn't
277+
* implemented. Since KVM's ability to emulate HPMN=0 does not directly
278+
* depend on hardware (all PMU registers are trapped), make the
279+
* implementation choice that all counters are included in the second
280+
* range reserved for EL2/EL3.
281+
*/
282+
hpmn = SYS_FIELD_GET(MDCR_EL2, HPMN, __vcpu_sys_reg(vcpu, MDCR_EL2));
283+
return idx >= hpmn;
284+
}
285+
268286
u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
269287
{
270288
u64 val = FIELD_GET(ARMV8_PMU_PMCR_N, kvm_vcpu_read_pmcr(vcpu));

‎include/kvm/arm_pmu.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ int kvm_arm_set_default_pmu(struct kvm *kvm);
9696
u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm);
9797

9898
u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu);
99+
bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx);
99100
#else
100101
struct kvm_pmu {
101102
};
@@ -187,6 +188,11 @@ static inline u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu)
187188
return 0;
188189
}
189190

191+
static inline bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx)
192+
{
193+
return false;
194+
}
195+
190196
#endif
191197

192198
#endif

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