@@ -54,10 +54,12 @@ struct clk_imx8_acm_sel {
5454 * struct imx8_acm_soc_data - soc specific data
5555 * @sels: pointer to struct clk_imx8_acm_sel
5656 * @num_sels: numbers of items
57+ * @mclk_sels: pointer to imx8qm/qxp/dxl_mclk_sels
5758 */
5859struct imx8_acm_soc_data {
5960 struct clk_imx8_acm_sel * sels ;
6061 unsigned int num_sels ;
62+ struct clk_parent_data * mclk_sels ;
6163};
6264
6365/**
@@ -111,11 +113,14 @@ static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
111113 { .fw_name = "sai6_rx_bclk" },
112114};
113115
114- static const struct clk_parent_data imx8qm_mclk_sels [] = {
116+ #define ACM_AUD_CLK0_SEL_INDEX 2
117+ #define ACM_AUD_CLK1_SEL_INDEX 3
118+
119+ static struct clk_parent_data imx8qm_mclk_sels [] = {
115120 { .fw_name = "aud_pll_div_clk0_lpcg_clk" },
116121 { .fw_name = "aud_pll_div_clk1_lpcg_clk" },
117- { . fw_name = "acm_aud_clk0_sel" },
118- { . fw_name = "acm_aud_clk1_sel" },
122+ { }, /* clk_hw pointer of "acm_aud_clk0_sel" */
123+ { }, /* clk_hw pointer of "acm_aud_clk1_sel" */
119124};
120125
121126static const struct clk_parent_data imx8qm_asrc_mux_clk_sels [] = {
@@ -176,11 +181,11 @@ static const struct clk_parent_data imx8qxp_mclk_out_sels[] = {
176181 { .fw_name = "sai4_rx_bclk" },
177182};
178183
179- static const struct clk_parent_data imx8qxp_mclk_sels [] = {
184+ static struct clk_parent_data imx8qxp_mclk_sels [] = {
180185 { .fw_name = "aud_pll_div_clk0_lpcg_clk" },
181186 { .fw_name = "aud_pll_div_clk1_lpcg_clk" },
182- { . fw_name = "acm_aud_clk0_sel" },
183- { . fw_name = "acm_aud_clk1_sel" },
187+ { }, /* clk_hw pointer of "acm_aud_clk0_sel" */
188+ { }, /* clk_hw pointer of "acm_aud_clk1_sel" */
184189};
185190
186191static struct clk_imx8_acm_sel imx8qxp_sels [] = {
@@ -228,11 +233,11 @@ static const struct clk_parent_data imx8dxl_mclk_out_sels[] = {
228233 { .index = -1 },
229234};
230235
231- static const struct clk_parent_data imx8dxl_mclk_sels [] = {
236+ static struct clk_parent_data imx8dxl_mclk_sels [] = {
232237 { .fw_name = "aud_pll_div_clk0_lpcg_clk" },
233238 { .fw_name = "aud_pll_div_clk1_lpcg_clk" },
234- { . fw_name = "acm_aud_clk0_sel" },
235- { . fw_name = "acm_aud_clk1_sel" },
239+ { }, /* clk_hw pointer of "acm_aud_clk0_sel" */
240+ { }, /* clk_hw pointer of "acm_aud_clk1_sel" */
236241};
237242
238243static struct clk_imx8_acm_sel imx8dxl_sels [] = {
@@ -375,6 +380,18 @@ static int imx8_acm_clk_probe(struct platform_device *pdev)
375380 imx_check_clk_hws (hws , IMX_ADMA_ACM_CLK_END );
376381 goto err_clk_register ;
377382 }
383+
384+ /*
385+ * The IMX_ADMA_ACM_AUD_CLK0_SEL and IMX_ADMA_ACM_AUD_CLK1_SEL are
386+ * registered first. After registration, update the clk_hw pointer
387+ * to imx8qm/qxp/dxl_mclk_sels structures.
388+ */
389+ if (sels [i ].clkid == IMX_ADMA_ACM_AUD_CLK0_SEL )
390+ priv -> soc_data -> mclk_sels [ACM_AUD_CLK0_SEL_INDEX ].hw =
391+ hws [IMX_ADMA_ACM_AUD_CLK0_SEL ];
392+ if (sels [i ].clkid == IMX_ADMA_ACM_AUD_CLK1_SEL )
393+ priv -> soc_data -> mclk_sels [ACM_AUD_CLK1_SEL_INDEX ].hw =
394+ hws [IMX_ADMA_ACM_AUD_CLK1_SEL ];
378395 }
379396
380397 ret = devm_of_clk_add_hw_provider (dev , of_clk_hw_onecell_get , clk_hw_data );
@@ -406,16 +423,19 @@ static void imx8_acm_clk_remove(struct platform_device *pdev)
406423static const struct imx8_acm_soc_data imx8qm_acm_data = {
407424 .sels = imx8qm_sels ,
408425 .num_sels = ARRAY_SIZE (imx8qm_sels ),
426+ .mclk_sels = imx8qm_mclk_sels ,
409427};
410428
411429static const struct imx8_acm_soc_data imx8qxp_acm_data = {
412430 .sels = imx8qxp_sels ,
413431 .num_sels = ARRAY_SIZE (imx8qxp_sels ),
432+ .mclk_sels = imx8qxp_mclk_sels ,
414433};
415434
416435static const struct imx8_acm_soc_data imx8dxl_acm_data = {
417436 .sels = imx8dxl_sels ,
418437 .num_sels = ARRAY_SIZE (imx8dxl_sels ),
438+ .mclk_sels = imx8dxl_mclk_sels ,
419439};
420440
421441static const struct of_device_id imx8_acm_match [] = {
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