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clk: sophgo: Add clock support for CV1810 SoC
Add clock definition and init code for CV1810 SoC. Signed-off-by: Inochi Amaoto <[email protected]> Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV180X-Clock-v1.xlsx Link: https://lore.kernel.org/r/IA1PR20MB495357FB5EEA1623DAB08C94BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/sophgo/clk-cv1800.c‎

Lines changed: 195 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -631,6 +631,10 @@ static const struct clk_parent_data clk_vip_sys_parents[] = {
631631
{ .hw = &clk_disppll.common.hw },
632632
{ .hw = &clk_fpll.common.hw },
633633
};
634+
static const struct clk_parent_data clk_disp_vip_parents[] = {
635+
{ .index = 0 },
636+
{ .hw = &clk_disppll.common.hw },
637+
};
634638

635639
static CV1800_BYPASS_DIV(clk_dsi_esc, clk_bypass_axi6_bus_parents,
636640
REG_CLK_EN_2, 3,
@@ -660,6 +664,11 @@ static CV1800_BYPASS_MUX(clk_src_vip_sys_1, clk_vip_sys_parents,
660664
REG_DIV_CLK_SRC_VIP_SYS_1, 8, 2,
661665
REG_CLK_BYP_0, 24,
662666
0);
667+
static CV1800_BYPASS_DIV(clk_disp_src_vip, clk_disp_vip_parents,
668+
REG_CLK_EN_2, 7,
669+
REG_DIV_CLK_DISP_SRC_VIP, 16, 4, 8, CV1800_DIV_FLAG,
670+
REG_CLK_BYP_0, 25,
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0);
663672
static CV1800_BYPASS_MUX(clk_src_vip_sys_2, clk_vip_sys_parents,
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REG_CLK_EN_3, 29,
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REG_DIV_CLK_SRC_VIP_SYS_2, 16, 4, 2, CV1800_DIV_FLAG,
@@ -1243,6 +1252,191 @@ static const struct cv1800_clk_desc cv1800_desc = {
12431252
.pre_init = cv1800_pre_init,
12441253
};
12451254

1255+
static struct clk_hw_onecell_data cv1810_hw_clks = {
1256+
.num = CV1810_CLK_MAX,
1257+
.hws = {
1258+
[CLK_MPLL] = &clk_mpll.common.hw,
1259+
[CLK_TPLL] = &clk_tpll.common.hw,
1260+
[CLK_FPLL] = &clk_fpll.common.hw,
1261+
[CLK_MIPIMPLL] = &clk_mipimpll.common.hw,
1262+
[CLK_A0PLL] = &clk_a0pll.common.hw,
1263+
[CLK_DISPPLL] = &clk_disppll.common.hw,
1264+
[CLK_CAM0PLL] = &clk_cam0pll.common.hw,
1265+
[CLK_CAM1PLL] = &clk_cam1pll.common.hw,
1266+
1267+
[CLK_MIPIMPLL_D3] = &clk_mipimpll_d3.common.hw,
1268+
[CLK_CAM0PLL_D2] = &clk_cam0pll_d2.common.hw,
1269+
[CLK_CAM0PLL_D3] = &clk_cam0pll_d3.common.hw,
1270+
1271+
[CLK_TPU] = &clk_tpu.mux.common.hw,
1272+
[CLK_TPU_FAB] = &clk_tpu_fab.common.hw,
1273+
[CLK_AHB_ROM] = &clk_ahb_rom.common.hw,
1274+
[CLK_DDR_AXI_REG] = &clk_ddr_axi_reg.common.hw,
1275+
[CLK_RTC_25M] = &clk_rtc_25m.common.hw,
1276+
[CLK_SRC_RTC_SYS_0] = &clk_src_rtc_sys_0.div.common.hw,
1277+
[CLK_TEMPSEN] = &clk_tempsen.common.hw,
1278+
[CLK_SARADC] = &clk_saradc.common.hw,
1279+
[CLK_EFUSE] = &clk_efuse.common.hw,
1280+
[CLK_APB_EFUSE] = &clk_apb_efuse.common.hw,
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[CLK_DEBUG] = &clk_debug.common.hw,
1282+
[CLK_AP_DEBUG] = &clk_ap_debug.div.common.hw,
1283+
[CLK_XTAL_MISC] = &clk_xtal_misc.common.hw,
1284+
[CLK_AXI4_EMMC] = &clk_axi4_emmc.common.hw,
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[CLK_EMMC] = &clk_emmc.mux.common.hw,
1286+
[CLK_EMMC_100K] = &clk_emmc_100k.common.hw,
1287+
[CLK_AXI4_SD0] = &clk_axi4_sd0.common.hw,
1288+
[CLK_SD0] = &clk_sd0.mux.common.hw,
1289+
[CLK_SD0_100K] = &clk_sd0_100k.common.hw,
1290+
[CLK_AXI4_SD1] = &clk_axi4_sd1.common.hw,
1291+
[CLK_SD1] = &clk_sd1.mux.common.hw,
1292+
[CLK_SD1_100K] = &clk_sd1_100k.common.hw,
1293+
[CLK_SPI_NAND] = &clk_spi_nand.mux.common.hw,
1294+
[CLK_ETH0_500M] = &clk_eth0_500m.div.common.hw,
1295+
[CLK_AXI4_ETH0] = &clk_axi4_eth0.common.hw,
1296+
[CLK_ETH1_500M] = &clk_eth1_500m.div.common.hw,
1297+
[CLK_AXI4_ETH1] = &clk_axi4_eth1.common.hw,
1298+
[CLK_APB_GPIO] = &clk_apb_gpio.common.hw,
1299+
[CLK_APB_GPIO_INTR] = &clk_apb_gpio_intr.common.hw,
1300+
[CLK_GPIO_DB] = &clk_gpio_db.common.hw,
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[CLK_AHB_SF] = &clk_ahb_sf.common.hw,
1302+
[CLK_AHB_SF1] = &clk_ahb_sf1.common.hw,
1303+
[CLK_A24M] = &clk_a24m.common.hw,
1304+
[CLK_AUDSRC] = &clk_audsrc.mux.common.hw,
1305+
[CLK_APB_AUDSRC] = &clk_apb_audsrc.common.hw,
1306+
[CLK_SDMA_AXI] = &clk_sdma_axi.common.hw,
1307+
[CLK_SDMA_AUD0] = &clk_sdma_aud0.mux.common.hw,
1308+
[CLK_SDMA_AUD1] = &clk_sdma_aud1.mux.common.hw,
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[CLK_SDMA_AUD2] = &clk_sdma_aud2.mux.common.hw,
1310+
[CLK_SDMA_AUD3] = &clk_sdma_aud3.mux.common.hw,
1311+
[CLK_I2C] = &clk_i2c.div.common.hw,
1312+
[CLK_APB_I2C] = &clk_apb_i2c.common.hw,
1313+
[CLK_APB_I2C0] = &clk_apb_i2c0.common.hw,
1314+
[CLK_APB_I2C1] = &clk_apb_i2c1.common.hw,
1315+
[CLK_APB_I2C2] = &clk_apb_i2c2.common.hw,
1316+
[CLK_APB_I2C3] = &clk_apb_i2c3.common.hw,
1317+
[CLK_APB_I2C4] = &clk_apb_i2c4.common.hw,
1318+
[CLK_APB_WDT] = &clk_apb_wdt.common.hw,
1319+
[CLK_PWM_SRC] = &clk_pwm_src.mux.common.hw,
1320+
[CLK_PWM] = &clk_pwm.common.hw,
1321+
[CLK_SPI] = &clk_spi.div.common.hw,
1322+
[CLK_APB_SPI0] = &clk_apb_spi0.common.hw,
1323+
[CLK_APB_SPI1] = &clk_apb_spi1.common.hw,
1324+
[CLK_APB_SPI2] = &clk_apb_spi2.common.hw,
1325+
[CLK_APB_SPI3] = &clk_apb_spi3.common.hw,
1326+
[CLK_1M] = &clk_1m.common.hw,
1327+
[CLK_CAM0_200] = &clk_cam0_200.mux.common.hw,
1328+
[CLK_PM] = &clk_pm.common.hw,
1329+
[CLK_TIMER0] = &clk_timer0.common.hw,
1330+
[CLK_TIMER1] = &clk_timer1.common.hw,
1331+
[CLK_TIMER2] = &clk_timer2.common.hw,
1332+
[CLK_TIMER3] = &clk_timer3.common.hw,
1333+
[CLK_TIMER4] = &clk_timer4.common.hw,
1334+
[CLK_TIMER5] = &clk_timer5.common.hw,
1335+
[CLK_TIMER6] = &clk_timer6.common.hw,
1336+
[CLK_TIMER7] = &clk_timer7.common.hw,
1337+
[CLK_UART0] = &clk_uart0.common.hw,
1338+
[CLK_APB_UART0] = &clk_apb_uart0.common.hw,
1339+
[CLK_UART1] = &clk_uart1.common.hw,
1340+
[CLK_APB_UART1] = &clk_apb_uart1.common.hw,
1341+
[CLK_UART2] = &clk_uart2.common.hw,
1342+
[CLK_APB_UART2] = &clk_apb_uart2.common.hw,
1343+
[CLK_UART3] = &clk_uart3.common.hw,
1344+
[CLK_APB_UART3] = &clk_apb_uart3.common.hw,
1345+
[CLK_UART4] = &clk_uart4.common.hw,
1346+
[CLK_APB_UART4] = &clk_apb_uart4.common.hw,
1347+
[CLK_APB_I2S0] = &clk_apb_i2s0.common.hw,
1348+
[CLK_APB_I2S1] = &clk_apb_i2s1.common.hw,
1349+
[CLK_APB_I2S2] = &clk_apb_i2s2.common.hw,
1350+
[CLK_APB_I2S3] = &clk_apb_i2s3.common.hw,
1351+
[CLK_AXI4_USB] = &clk_axi4_usb.common.hw,
1352+
[CLK_APB_USB] = &clk_apb_usb.common.hw,
1353+
[CLK_USB_125M] = &clk_usb_125m.div.common.hw,
1354+
[CLK_USB_33K] = &clk_usb_33k.common.hw,
1355+
[CLK_USB_12M] = &clk_usb_12m.div.common.hw,
1356+
[CLK_AXI4] = &clk_axi4.mux.common.hw,
1357+
[CLK_AXI6] = &clk_axi6.div.common.hw,
1358+
[CLK_DSI_ESC] = &clk_dsi_esc.div.common.hw,
1359+
[CLK_AXI_VIP] = &clk_axi_vip.mux.common.hw,
1360+
[CLK_SRC_VIP_SYS_0] = &clk_src_vip_sys_0.mux.common.hw,
1361+
[CLK_SRC_VIP_SYS_1] = &clk_src_vip_sys_1.mux.common.hw,
1362+
[CLK_SRC_VIP_SYS_2] = &clk_src_vip_sys_2.mux.common.hw,
1363+
[CLK_SRC_VIP_SYS_3] = &clk_src_vip_sys_3.mux.common.hw,
1364+
[CLK_SRC_VIP_SYS_4] = &clk_src_vip_sys_4.mux.common.hw,
1365+
[CLK_CSI_BE_VIP] = &clk_csi_be_vip.common.hw,
1366+
[CLK_CSI_MAC0_VIP] = &clk_csi_mac0_vip.common.hw,
1367+
[CLK_CSI_MAC1_VIP] = &clk_csi_mac1_vip.common.hw,
1368+
[CLK_CSI_MAC2_VIP] = &clk_csi_mac2_vip.common.hw,
1369+
[CLK_CSI0_RX_VIP] = &clk_csi0_rx_vip.common.hw,
1370+
[CLK_CSI1_RX_VIP] = &clk_csi1_rx_vip.common.hw,
1371+
[CLK_ISP_TOP_VIP] = &clk_isp_top_vip.common.hw,
1372+
[CLK_IMG_D_VIP] = &clk_img_d_vip.common.hw,
1373+
[CLK_IMG_V_VIP] = &clk_img_v_vip.common.hw,
1374+
[CLK_SC_TOP_VIP] = &clk_sc_top_vip.common.hw,
1375+
[CLK_SC_D_VIP] = &clk_sc_d_vip.common.hw,
1376+
[CLK_SC_V1_VIP] = &clk_sc_v1_vip.common.hw,
1377+
[CLK_SC_V2_VIP] = &clk_sc_v2_vip.common.hw,
1378+
[CLK_SC_V3_VIP] = &clk_sc_v3_vip.common.hw,
1379+
[CLK_DWA_VIP] = &clk_dwa_vip.common.hw,
1380+
[CLK_BT_VIP] = &clk_bt_vip.common.hw,
1381+
[CLK_DISP_VIP] = &clk_disp_vip.common.hw,
1382+
[CLK_DSI_MAC_VIP] = &clk_dsi_mac_vip.common.hw,
1383+
[CLK_LVDS0_VIP] = &clk_lvds0_vip.common.hw,
1384+
[CLK_LVDS1_VIP] = &clk_lvds1_vip.common.hw,
1385+
[CLK_PAD_VI_VIP] = &clk_pad_vi_vip.common.hw,
1386+
[CLK_PAD_VI1_VIP] = &clk_pad_vi1_vip.common.hw,
1387+
[CLK_PAD_VI2_VIP] = &clk_pad_vi2_vip.common.hw,
1388+
[CLK_CFG_REG_VIP] = &clk_cfg_reg_vip.common.hw,
1389+
[CLK_VIP_IP0] = &clk_vip_ip0.common.hw,
1390+
[CLK_VIP_IP1] = &clk_vip_ip1.common.hw,
1391+
[CLK_VIP_IP2] = &clk_vip_ip2.common.hw,
1392+
[CLK_VIP_IP3] = &clk_vip_ip3.common.hw,
1393+
[CLK_IVE_VIP] = &clk_ive_vip.common.hw,
1394+
[CLK_RAW_VIP] = &clk_raw_vip.common.hw,
1395+
[CLK_OSDC_VIP] = &clk_osdc_vip.common.hw,
1396+
[CLK_CAM0_VIP] = &clk_cam0_vip.common.hw,
1397+
[CLK_AXI_VIDEO_CODEC] = &clk_axi_video_codec.mux.common.hw,
1398+
[CLK_VC_SRC0] = &clk_vc_src0.mux.common.hw,
1399+
[CLK_VC_SRC1] = &clk_vc_src1.div.common.hw,
1400+
[CLK_VC_SRC2] = &clk_vc_src2.div.common.hw,
1401+
[CLK_H264C] = &clk_h264c.common.hw,
1402+
[CLK_APB_H264C] = &clk_apb_h264c.common.hw,
1403+
[CLK_H265C] = &clk_h265c.common.hw,
1404+
[CLK_APB_H265C] = &clk_apb_h265c.common.hw,
1405+
[CLK_JPEG] = &clk_jpeg.common.hw,
1406+
[CLK_APB_JPEG] = &clk_apb_jpeg.common.hw,
1407+
[CLK_CAM0] = &clk_cam0.common.hw,
1408+
[CLK_CAM1] = &clk_cam1.common.hw,
1409+
[CLK_WGN] = &clk_wgn.common.hw,
1410+
[CLK_WGN0] = &clk_wgn0.common.hw,
1411+
[CLK_WGN1] = &clk_wgn1.common.hw,
1412+
[CLK_WGN2] = &clk_wgn2.common.hw,
1413+
[CLK_KEYSCAN] = &clk_keyscan.common.hw,
1414+
[CLK_CFG_REG_VC] = &clk_cfg_reg_vc.common.hw,
1415+
[CLK_C906_0] = &clk_c906_0.common.hw,
1416+
[CLK_C906_1] = &clk_c906_1.common.hw,
1417+
[CLK_A53] = &clk_a53.common.hw,
1418+
[CLK_CPU_AXI0] = &clk_cpu_axi0.div.common.hw,
1419+
[CLK_CPU_GIC] = &clk_cpu_gic.div.common.hw,
1420+
[CLK_XTAL_AP] = &clk_xtal_ap.common.hw,
1421+
[CLK_DISP_SRC_VIP] = &clk_disp_src_vip.div.common.hw,
1422+
},
1423+
};
1424+
1425+
static int cv1810_pre_init(struct device *dev, void __iomem *base,
1426+
struct cv1800_clk_ctrl *ctrl,
1427+
const struct cv1800_clk_desc *desc)
1428+
{
1429+
cv18xx_clk_disable_a53(base);
1430+
cv18xx_clk_disable_auto_pd(base);
1431+
1432+
return 0;
1433+
}
1434+
1435+
static const struct cv1800_clk_desc cv1810_desc = {
1436+
.clks_data = &cv1810_hw_clks,
1437+
.pre_init = cv1810_pre_init,
1438+
};
1439+
12461440
static int cv1800_clk_init_ctrl(struct device *dev, void __iomem *reg,
12471441
struct cv1800_clk_ctrl *ctrl,
12481442
const struct cv1800_clk_desc *desc)
@@ -1311,6 +1505,7 @@ static int cv1800_clk_probe(struct platform_device *pdev)
13111505

13121506
static const struct of_device_id cv1800_clk_ids[] = {
13131507
{ .compatible = "sophgo,cv1800-clk", .data = &cv1800_desc },
1508+
{ .compatible = "sophgo,cv1810-clk", .data = &cv1810_desc },
13141509
{ }
13151510
};
13161511
MODULE_DEVICE_TABLE(of, cv1800_clk_ids);

‎drivers/clk/sophgo/clk-cv1800.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <dt-bindings/clock/sophgo,cv1800.h>
1010

1111
#define CV1800_CLK_MAX (CLK_XTAL_AP + 1)
12+
#define CV1810_CLK_MAX (CLK_DISP_SRC_VIP + 1)
1213

1314
#define REG_PLL_G2_CTRL 0x800
1415
#define REG_PLL_G2_STATUS 0x804

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