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Merge tag 'stm32-bus-firewall-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/drivers
STM32 Firewall bus for v6.10, round 1 Highlights: --------- Introduce STM32 Firewall framework for STM32MP1x and STM32MP2x platforms. STM32MP1x(ETZPC) and STM32MP2x(RIFSC) Firewall controllers register to the framework to offer firewall services such as access granting. This series of patches is a new approach on the previous STM32 system bus, history is available here: https://lore.kernel.org/lkml/20230127164040.1047583/ The need for such framework arises from the fact that there are now multiple hardware firewalls implemented across multiple products. Drivers are shared between different products, using the same code. When it comes to firewalls, the purpose mostly stays the same: Protect hardware resources. But the implementation differs, and there are multiple types of firewalls: peripheral, memory, ... Some hardware firewall controllers such as the RIFSC implemented on STM32MP2x platforms may require to take ownership of a resource before being able to use it, hence the requirement for firewall services to take/release the ownership of such resources. On the other hand, hardware firewall configurations are becoming more and more complex. These mecanisms prevent platform crashes or other firewall-related incoveniences by denying access to some resources. The stm32 firewall framework offers an API that is defined in firewall controllers drivers to best fit the specificity of each firewall. For every peripherals protected by either the ETZPC or the RIFSC, the firewall framework checks the firewall controlelr registers to see if the peripheral's access is granted to the Linux kernel. If not, the peripheral is configured as secure, the node is marked populated, so that the driver is not probed for that device. The firewall framework relies on the access-controller device tree binding. It is used by peripherals to reference a domain access controller. In this case a firewall controller. The bus uses the ID referenced by the access-controller property to know where to look in the firewall to get the security configuration for the peripheral. This allows a device tree description rather than a hardcoded peripheral table in the bus driver. The STM32 ETZPC device is responsible for filtering accesses based on security level, or co-processor isolation for any resource connected to it. The RIFSC is responsible for filtering accesses based on Compartment ID / security level / privilege level for any resource connected to it. * tag 'stm32-bus-firewall-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: bus: stm32_firewall: fix off by one in stm32_firewall_get_firewall() bus: etzpc: introduce ETZPC firewall controller driver bus: rifsc: introduce RIFSC firewall controller driver of: property: fw_devlink: Add support for "access-controller" firewall: introduce stm32_firewall framework dt-bindings: bus: document ETZPC dt-bindings: bus: document RIFSC dt-bindings: treewide: add access-controllers description dt-bindings: document generic access controllers Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎Documentation/devicetree/bindings/access-controllers/access-controllers.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic Domain Access Controllers
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maintainers:
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- Oleksii Moisieiev <[email protected]>
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description: |+
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Common access controllers properties
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Access controllers are in charge of stating which of the hardware blocks under
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their responsibility (their domain) can be accesssed by which compartment. A
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compartment can be a cluster of CPUs (or coprocessors), a range of addresses
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or a group of hardware blocks. An access controller's domain is the set of
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resources covered by the access controller.
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This device tree binding can be used to bind devices to their access
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controller provided by access-controllers property. In this case, the device
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is a consumer and the access controller is the provider.
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An access controller can be represented by any node in the device tree and
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can provide one or more configuration parameters, needed to control parameters
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of the consumer device. A consumer node can refer to the provider by phandle
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and a set of phandle arguments, specified by '#access-controller-cells'
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property in the access controller node.
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Access controllers are typically used to set/read the permissions of a
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hardware block and grant access to it. Any of which depends on the access
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controller. The capabilities of each access controller are defined by the
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binding of the access controller device.
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Each node can be a consumer for the several access controllers.
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# always select the core schema
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select: true
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properties:
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"#access-controller-cells":
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description:
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Number of cells in an access-controllers specifier;
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Can be any value as specified by device tree binding documentation
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of a particular provider. The node is an access controller.
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access-controller-names:
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$ref: /schemas/types.yaml#/definitions/string-array
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description:
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A list of access-controllers names, sorted in the same order as
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access-controllers entries. Consumer drivers will use
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access-controller-names to match with existing access-controllers entries.
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access-controllers:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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A list of access controller specifiers, as defined by the
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bindings of the access-controllers provider.
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additionalProperties: true
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examples:
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- |
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clock_controller: access-controllers@50000 {
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reg = <0x50000 0x400>;
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#access-controller-cells = <2>;
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};
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bus_controller: bus@60000 {
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reg = <0x60000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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#access-controller-cells = <3>;
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uart4: serial@60100 {
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reg = <0x60100 0x400>;
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clocks = <&clk_serial>;
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access-controllers = <&clock_controller 1 2>,
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<&bus_controller 1 3 5>;
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access-controller-names = "clock", "bus";
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};
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};

‎Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32 Extended TrustZone protection controller
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description: |
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The ETZPC configures TrustZone security in a SoC having bus masters and
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devices with programmable-security attributes (securable resources).
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maintainers:
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- Gatien Chevallier <[email protected]>
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select:
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properties:
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compatible:
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contains:
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const: st,stm32-etzpc
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required:
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- compatible
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properties:
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compatible:
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items:
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- const: st,stm32-etzpc
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- const: simple-bus
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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"#access-controller-cells":
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const: 1
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description:
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Contains the firewall ID associated to the peripheral.
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patternProperties:
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"^.*@[0-9a-f]+$":
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description: Peripherals
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type: object
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additionalProperties: true
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required:
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- access-controllers
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- "#access-controller-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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// In this example, the usart2 device refers to rifsc as its access
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// controller.
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// Access rights are verified before creating devices.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp13-clks.h>
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#include <dt-bindings/reset/stm32mp13-resets.h>
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etzpc: bus@5c007000 {
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compatible = "st,stm32-etzpc", "simple-bus";
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reg = <0x5c007000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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#access-controller-cells = <1>;
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ranges;
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usart2: serial@4c001000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4c001000 0x400>;
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interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART2_K>;
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resets = <&rcc USART2_R>;
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wakeup-source;
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dmas = <&dmamux1 43 0x400 0x5>,
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<&dmamux1 44 0x400 0x1>;
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dma-names = "rx", "tx";
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access-controllers = <&etzpc 17>;
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};
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};

‎Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32 Resource isolation framework security controller
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maintainers:
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- Gatien Chevallier <[email protected]>
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description: |
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Resource isolation framework (RIF) is a comprehensive set of hardware blocks
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designed to enforce and manage isolation of STM32 hardware resources like
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memory and peripherals.
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The RIFSC (RIF security controller) is composed of three sets of registers,
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each managing a specific set of hardware resources:
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- RISC registers associated with RISUP logic (resource isolation device unit
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for peripherals), assign all non-RIF aware peripherals to zero, one or
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any security domains (secure, privilege, compartment).
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- RIMC registers: associated with RIMU logic (resource isolation master
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unit), assign all non RIF-aware bus master to one security domain by
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setting secure, privileged and compartment information on the system bus.
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Alternatively, the RISUP logic controlling the device port access to a
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peripheral can assign target bus attributes to this peripheral master port
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(supported attribute: CID).
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- RISC registers associated with RISAL logic (resource isolation device unit
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for address space - Lite version), assign address space subregions to one
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security domains (secure, privilege, compartment).
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select:
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properties:
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compatible:
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contains:
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const: st,stm32mp25-rifsc
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required:
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- compatible
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properties:
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compatible:
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items:
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- const: st,stm32mp25-rifsc
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- const: simple-bus
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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"#access-controller-cells":
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const: 1
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description:
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Contains the firewall ID associated to the peripheral.
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patternProperties:
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"^.*@[0-9a-f]+$":
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description: Peripherals
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type: object
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additionalProperties: true
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required:
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- access-controllers
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- "#access-controller-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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// In this example, the usart2 device refers to rifsc as its domain
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// controller.
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// Access rights are verified before creating devices.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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rifsc: bus@42080000 {
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compatible = "st,stm32mp25-rifsc", "simple-bus";
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reg = <0x42080000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#access-controller-cells = <1>;
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ranges;
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usart2: serial@400e0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400e0000 0x400>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ck_flexgen_08>;
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access-controllers = <&rifsc 32>;
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};
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};

‎Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml‎

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power-domains:
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maxItems: 1
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access-controllers:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml‎

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power-domains:
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maxItems: 1
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access-controllers:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/dma/st,stm32-dma.yaml‎

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description: if defined, it indicates that the controller
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supports memory-to-memory transfer
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access-controllers:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml‎

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resets:
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maxItems: 1
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access-controllers:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml‎

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wakeup-source: true
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access-controllers:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml‎

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'#size-cells':
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const: 0
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access-controllers:
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minItems: 1
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maxItems: 2
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allOf:
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- if:
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properties:

‎Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml‎

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If not, SPI CLKOUT frequency will not be accurate.
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maximum: 20000000
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access-controllers:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg

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