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geertugeertu
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pinctrl: renesas: r8a779g0: Fix FXR_TXEN[AB] suffixes
The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series Hardware User's Manual still has two alternate pins named both "FXR_TXEN[AB]". To differentiate, the pin control driver uses "FXR_TXEN[AB]" and "FXR_TXEN[AB]_X", which were considered temporary names until the conflict was sorted out. Fix this by adopting R-Car V4M naming: - Rename "FXR_TXEN[AB]" to "FXR_TXEN[AB]_A", - Rename "FXR_TXEN[AB]_X" to "FXR_TXEN[AB]_B". Fixes: ad9bb2f ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 1c2646b ("pinctrl: renesas: r8a779g0: Add missing FlexRay") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/5e1e9abb46c311d4c54450d991072d6d0e66f14c.1717754960.git.geert+renesas@glider.be
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‎drivers/pinctrl/renesas/pfc-r8a779g0.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -122,11 +122,11 @@
122122
#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
123123
#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
124124
#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
125-
#define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20)
125+
#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)
126126
#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
127127
#define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
128128
#define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
129-
#define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4)
129+
#define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)
130130
#define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
131131

132132
/* GPSR3 */
@@ -340,18 +340,18 @@
340340
/* SR2 */
341341
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
342342
#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343-
#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343+
#define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344344
#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX_A) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345345
#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX_A) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346346
#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347-
#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347+
#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348348
#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349349
#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350350

351351
/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
352352
#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353-
#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354-
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353+
#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354+
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355355
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356356
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357357
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -891,7 +891,7 @@ static const u16 pinmux_data[] = {
891891
PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
892892
PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A),
893893

894-
PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
894+
PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),
895895
PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
896896
PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A),
897897

@@ -905,7 +905,7 @@ static const u16 pinmux_data[] = {
905905

906906
PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
907907

908-
PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N),
908+
PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A),
909909

910910
PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
911911

@@ -919,10 +919,10 @@ static const u16 pinmux_data[] = {
919919
PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A),
920920

921921
PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
922-
PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_X),
922+
PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B),
923923

924924
PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
925-
PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_X),
925+
PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),
926926

927927
PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
928928
PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),

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