drm/nouveau/gsp: add hal for fifo.chan.doorbell_handle

The doorbell register on GB20x GPUs has additional fields.

Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Reviewed-by: Timur Tabi <[email protected]>
Tested-by: Timur Tabi <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>

Author: Ben Skeggs

drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h

@@ -6,6 +6,7 @@
 #include <core/enum.h>
 struct nvkm_cctx;
 struct nvkm_cgrp;
+struct nvkm_chan;
 struct nvkm_engn;
 struct nvkm_memory;
 struct nvkm_runl;
@@ -195,6 +196,7 @@ extern const struct nvkm_chan_func_ramfc gv100_chan_ramfc;
 
 void tu102_fifo_intr_ctxsw_timeout_info(struct nvkm_engn *, u32 info);
 extern const struct nvkm_fifo_func_mmu_fault tu102_fifo_mmu_fault;
+u32 tu102_chan_doorbell_handle(struct nvkm_chan *);
 
 int ga100_fifo_runl_ctor(struct nvkm_fifo *);
 int ga100_fifo_nonstall_ctor(struct nvkm_fifo *);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c

@@ -31,7 +31,7 @@
 
 #include <nvif/class.h>
 
-static u32
+u32
 tu102_chan_doorbell_handle(struct nvkm_chan *chan)
 {
 	return (chan->cgrp->runl->id << 16) | chan->id;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c

@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ ad10x_gpu = {
 
 	.fifo.chan = {
 		.class = AMPERE_CHANNEL_GPFIFO_A,
+		.doorbell_handle = tu102_chan_doorbell_handle,
 	},
 
 	.ce.class = AMPERE_DMA_COPY_B,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga100.c

@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ ga100_gpu = {
 
 	.fifo.chan = {
 		.class = AMPERE_CHANNEL_GPFIFO_A,
+		.doorbell_handle = tu102_chan_doorbell_handle,
 	},
 
 	.ce.class = AMPERE_DMA_COPY_A,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c

@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ ga1xx_gpu = {
 
 	.fifo.chan = {
 		.class = AMPERE_CHANNEL_GPFIFO_A,
+		.doorbell_handle = tu102_chan_doorbell_handle,
 	},
 
 	.ce.class = AMPERE_DMA_COPY_B,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gb10x.c

@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ gb10x_gpu = {
 
 	.fifo.chan = {
 		.class = BLACKWELL_CHANNEL_GPFIFO_A,
+		.doorbell_handle = tu102_chan_doorbell_handle,
 	},
 
 	.ce.class = BLACKWELL_DMA_COPY_A,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gh100.c

@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ gh100_gpu = {
 
 	.fifo.chan = {
 		.class = HOPPER_CHANNEL_GPFIFO_A,
+		.doorbell_handle = tu102_chan_doorbell_handle,
 	},
 
 	.ce.class = HOPPER_DMA_COPY_A,

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h

@@ -25,6 +25,7 @@ struct nvkm_rm_gpu {
 	struct {
 		struct {
 			u32 class;
+			u32 (*doorbell_handle)(struct nvkm_chan *);
 		} chan;
 	} fifo;
 

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c

@@ -41,7 +41,9 @@
 static u32
 r535_chan_doorbell_handle(struct nvkm_chan *chan)
 {
-	return (chan->cgrp->runl->id << 16) | chan->id;
+	struct nvkm_gsp *gsp = chan->rm.object.client->gsp;
+
+	return gsp->rm->gpu->fifo.chan.doorbell_handle(chan);
 }
 
 static void

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c

@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ tu1xx_gpu = {
 
 	.fifo.chan = {
 		.class = TURING_CHANNEL_GPFIFO_A,
+		.doorbell_handle = tu102_chan_doorbell_handle,
 	},
 
 	.ce.class = TURING_DMA_COPY_A,