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Alexandre Ghiti
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Merge patch series "riscv: add support for Zaamo and Zalrsc extensions"
Clément Léger <[email protected]> says: Since commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"), the A extension has been described as a set of instructions provided by Zaamo and Zalrsc. Add these two extensions. This series is based on the Zc one [1]. Link: https://lore.kernel.org/linux-riscv/[email protected]/ [1] * patches from https://lore.kernel.org/lkml/[email protected]/: dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description riscv: add parsing for Zaamo and Zalrsc extensions riscv: hwprobe: export Zaamo and Zalrsc extensions RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test Link: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Alexandre Ghiti <[email protected]>
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‎Documentation/arch/riscv/hwprobe.rst‎

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@@ -245,6 +245,14 @@ The following keys are defined:
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ratified in commit 98918c844281 ("Merge pull request #1217 from
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riscv/zawrs") of riscv-isa-manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as
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defined in the in the RISC-V ISA manual starting from commit e87412e621f1
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("integrate Zaamo and Zalrsc text (#1304)").
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* :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
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defined in the in the RISC-V ISA manual starting from commit e87412e621f1
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("integrate Zaamo and Zalrsc text (#1304)").
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* :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
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defined in version 1.0 of the RISC-V Pointer Masking extensions.
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‎Documentation/devicetree/bindings/riscv/extensions.yaml‎

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@@ -224,6 +224,12 @@ properties:
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as ratified at commit 4a69197e5617 ("Update to ratified state") of
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riscv-svvptc.
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- const: zaamo
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description: |
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The standard Zaamo extension for atomic memory operations as
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ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text
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(#1304)") of the unprivileged ISA specification.
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- const: zabha
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description: |
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The Zabha extension for Byte and Halfword Atomic Memory Operations
@@ -236,6 +242,12 @@ properties:
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is supported as ratified at commit 5059e0ca641c ("update to
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ratified") of the riscv-zacas.
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- const: zalrsc
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description: |
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The standard Zalrsc extension for load-reserved/store-conditional as
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ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text
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(#1304)") of the unprivileged ISA specification.
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- const: zawrs
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description: |
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The Zawrs extension for entering a low-power state or for trapping
@@ -718,6 +730,13 @@ properties:
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const: zfbfmin
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- contains:
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const: zvfbfmin
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# Zacas depends on Zaamo
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- if:
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contains:
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const: zacas
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then:
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contains:
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const: zaamo
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allOf:
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# Zcf extension does not exist on rv64

‎arch/riscv/include/asm/hwcap.h‎

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@@ -103,6 +103,8 @@
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#define RISCV_ISA_EXT_ZFBFMIN 94
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#define RISCV_ISA_EXT_ZVFBFMIN 95
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#define RISCV_ISA_EXT_ZVFBFWMA 96
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#define RISCV_ISA_EXT_ZAAMO 97
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#define RISCV_ISA_EXT_ZALRSC 98
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#define RISCV_ISA_EXT_XLINUXENVCFG 127
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‎arch/riscv/include/uapi/asm/hwprobe.h‎

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@@ -79,6 +79,8 @@ struct riscv_hwprobe {
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#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 53)
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#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 54)
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#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 55)
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#define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
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#define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)

‎arch/riscv/include/uapi/asm/kvm.h‎

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@@ -182,6 +182,8 @@ enum KVM_RISCV_ISA_EXT_ID {
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KVM_RISCV_ISA_EXT_SVVPTC,
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KVM_RISCV_ISA_EXT_ZABHA,
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KVM_RISCV_ISA_EXT_ZICCRSE,
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KVM_RISCV_ISA_EXT_ZAAMO,
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KVM_RISCV_ISA_EXT_ZALRSC,
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KVM_RISCV_ISA_EXT_MAX,
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};
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‎arch/riscv/kernel/cpufeature.c‎

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@@ -182,6 +182,11 @@ static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
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return 0;
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}
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static const unsigned int riscv_a_exts[] = {
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RISCV_ISA_EXT_ZAAMO,
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RISCV_ISA_EXT_ZALRSC,
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};
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static const unsigned int riscv_zk_bundled_exts[] = {
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RISCV_ISA_EXT_ZBKB,
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RISCV_ISA_EXT_ZBKC,
@@ -353,7 +358,7 @@ static const unsigned int riscv_c_exts[] = {
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const struct riscv_isa_ext_data riscv_isa_ext[] = {
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__RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
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__RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
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__RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a),
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__RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_a, riscv_a_exts),
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__RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
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__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
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__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
@@ -373,8 +378,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
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__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
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__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
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__RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
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__RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
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__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
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__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
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__RISCV_ISA_EXT_DATA(zalrsc, RISCV_ISA_EXT_ZALRSC),
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__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
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__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
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__RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends),

‎arch/riscv/kernel/sys_hwprobe.c‎

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@@ -95,7 +95,9 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
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* regardless of the kernel's configuration, as no other checks, besides
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* presence in the hart_isa bitmap, are made.
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*/
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EXT_KEY(ZAAMO);
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EXT_KEY(ZACAS);
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EXT_KEY(ZALRSC);
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EXT_KEY(ZAWRS);
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EXT_KEY(ZBA);
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EXT_KEY(ZBB);

‎arch/riscv/kvm/vcpu_onereg.c‎

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@@ -47,8 +47,10 @@ static const unsigned long kvm_isa_ext_arr[] = {
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KVM_ISA_EXT_ARR(SVNAPOT),
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KVM_ISA_EXT_ARR(SVPBMT),
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KVM_ISA_EXT_ARR(SVVPTC),
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KVM_ISA_EXT_ARR(ZAAMO),
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KVM_ISA_EXT_ARR(ZABHA),
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KVM_ISA_EXT_ARR(ZACAS),
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KVM_ISA_EXT_ARR(ZALRSC),
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KVM_ISA_EXT_ARR(ZAWRS),
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KVM_ISA_EXT_ARR(ZBA),
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KVM_ISA_EXT_ARR(ZBB),
@@ -149,8 +151,10 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
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case KVM_RISCV_ISA_EXT_SVINVAL:
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case KVM_RISCV_ISA_EXT_SVNAPOT:
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case KVM_RISCV_ISA_EXT_SVVPTC:
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case KVM_RISCV_ISA_EXT_ZAAMO:
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case KVM_RISCV_ISA_EXT_ZABHA:
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case KVM_RISCV_ISA_EXT_ZACAS:
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case KVM_RISCV_ISA_EXT_ZALRSC:
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case KVM_RISCV_ISA_EXT_ZAWRS:
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case KVM_RISCV_ISA_EXT_ZBA:
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case KVM_RISCV_ISA_EXT_ZBB:

‎tools/testing/selftests/kvm/riscv/get-reg-list.c‎

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@@ -53,8 +53,10 @@ bool filter_reg(__u64 reg)
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAAMO:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALRSC:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
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case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB:
@@ -434,8 +436,10 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
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KVM_ISA_EXT_ARR(SVNAPOT),
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KVM_ISA_EXT_ARR(SVPBMT),
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KVM_ISA_EXT_ARR(SVVPTC),
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KVM_ISA_EXT_ARR(ZAAMO),
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KVM_ISA_EXT_ARR(ZABHA),
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KVM_ISA_EXT_ARR(ZACAS),
442+
KVM_ISA_EXT_ARR(ZALRSC),
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KVM_ISA_EXT_ARR(ZAWRS),
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KVM_ISA_EXT_ARR(ZBA),
441445
KVM_ISA_EXT_ARR(ZBB),
@@ -974,8 +978,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
974978
KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
975979
KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
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KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC);
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KVM_ISA_EXT_SIMPLE_CONFIG(zaamo, ZAAMO);
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KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA);
978983
KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);
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KVM_ISA_EXT_SIMPLE_CONFIG(zalrsc, ZALRSC);
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KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);
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KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
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KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB);
@@ -1045,8 +1051,10 @@ struct vcpu_reg_list *vcpu_configs[] = {
10451051
&config_svnapot,
10461052
&config_svpbmt,
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&config_svvptc,
1054+
&config_zaamo,
10481055
&config_zabha,
10491056
&config_zacas,
1057+
&config_zalrsc,
10501058
&config_zawrs,
10511059
&config_zba,
10521060
&config_zbb,

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