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mm: introduce cpu_icache_is_aliasing() across all architectures
In commit eacd0e9 ("ARC: [mm] Lazy D-cache flush (non aliasing VIPT)"), arc adds the need to flush dcache to make icache see the code page change. This also requires special handling for clear_user_(high)page(). Introduce cpu_icache_is_aliasing() to make MM code query special clear_user_(high)page() easier. This will be used by the following commit. Link: https://lkml.kernel.org/r/[email protected] Fixes: 5708d96 ("mm: avoid zeroing user movable page twice with init_on_alloc=1") Signed-off-by: Zi Yan <[email protected]> Suggested-by: Mathieu Desnoyers <[email protected]> Reviewed-by: Mathieu Desnoyers <[email protected]> Acked-by: Vlastimil Babka <[email protected]> Cc: Alexander Potapenko <[email protected]> Cc: David Hildenbrand <[email protected]> Cc: Geert Uytterhoeven <[email protected]> Cc: John Hubbard <[email protected]> Cc: Kees Cook <[email protected]> Cc: Kefeng Wang <[email protected]> Cc: Matthew Wilcox <[email protected]> Cc: Miaohe Lin <[email protected]> Cc: Ryan Roberts <[email protected]> Cc: Vineet Gupta <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
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arch/arc/Kconfig

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config ARC
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def_bool y
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select ARC_TIMERS
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select ARCH_HAS_CPU_CACHE_ALIASING
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select ARCH_HAS_CACHE_LINE_SIZE
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select ARCH_HAS_DEBUG_VM_PGTABLE
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select ARCH_HAS_DMA_PREP_COHERENT

arch/arc/include/asm/cachetype.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARC_CACHETYPE_H
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#define __ASM_ARC_CACHETYPE_H
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#define cpu_dcache_is_aliasing() false
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#define cpu_icache_is_aliasing() true
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#endif

include/linux/cacheinfo.h

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#ifndef CONFIG_ARCH_HAS_CPU_CACHE_ALIASING
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#define cpu_dcache_is_aliasing() false
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#define cpu_icache_is_aliasing() cpu_dcache_is_aliasing()
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#else
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#include <asm/cachetype.h>
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#ifndef cpu_icache_is_aliasing
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#define cpu_icache_is_aliasing() cpu_dcache_is_aliasing()
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#endif
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#endif
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#endif /* _LINUX_CACHEINFO_H */

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