@@ -116,11 +116,13 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
116116 }
117117}
118118
119- static const char * config_id_to_str (__u64 id )
119+ static const char * config_id_to_str (const char * prefix , __u64 id )
120120{
121121 /* reg_off is the offset into struct kvm_riscv_config */
122122 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG );
123123
124+ assert ((id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CONFIG );
125+
124126 switch (reg_off ) {
125127 case KVM_REG_RISCV_CONFIG_REG (isa ):
126128 return "KVM_REG_RISCV_CONFIG_REG(isa)" ;
@@ -138,18 +140,16 @@ static const char *config_id_to_str(__u64 id)
138140 return "KVM_REG_RISCV_CONFIG_REG(satp_mode)" ;
139141 }
140142
141- /*
142- * Config regs would grow regularly with new pseudo reg added, so
143- * just show raw id to indicate a new pseudo config reg.
144- */
145- return strdup_printf ("KVM_REG_RISCV_CONFIG_REG(%lld) /* UNKNOWN */" , reg_off );
143+ return strdup_printf ("%lld /* UNKNOWN */" , reg_off );
146144}
147145
148146static const char * core_id_to_str (const char * prefix , __u64 id )
149147{
150148 /* reg_off is the offset into struct kvm_riscv_core */
151149 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE );
152150
151+ assert ((id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CORE );
152+
153153 switch (reg_off ) {
154154 case KVM_REG_RISCV_CORE_REG (regs .pc ):
155155 return "KVM_REG_RISCV_CORE_REG(regs.pc)" ;
@@ -180,8 +180,7 @@ static const char *core_id_to_str(const char *prefix, __u64 id)
180180 return "KVM_REG_RISCV_CORE_REG(mode)" ;
181181 }
182182
183- TEST_FAIL ("%s: Unknown core reg id: 0x%llx" , prefix , id );
184- return NULL ;
183+ return strdup_printf ("%lld /* UNKNOWN */" , reg_off );
185184}
186185
187186#define RISCV_CSR_GENERAL (csr ) \
@@ -219,8 +218,7 @@ static const char *general_csr_id_to_str(__u64 reg_off)
219218 return RISCV_CSR_GENERAL (senvcfg );
220219 }
221220
222- TEST_FAIL ("Unknown general csr reg: 0x%llx" , reg_off );
223- return NULL ;
221+ return strdup_printf ("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */" , reg_off );
224222}
225223
226224static const char * aia_csr_id_to_str (__u64 reg_off )
@@ -243,8 +241,7 @@ static const char *aia_csr_id_to_str(__u64 reg_off)
243241 return RISCV_CSR_AIA (iprio2h );
244242 }
245243
246- TEST_FAIL ("Unknown aia csr reg: 0x%llx" , reg_off );
247- return NULL ;
244+ return strdup_printf ("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */" , reg_off );
248245}
249246
250247static const char * smstateen_csr_id_to_str (__u64 reg_off )
@@ -264,6 +261,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
264261 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR );
265262 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK ;
266263
264+ assert ((id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CSR );
265+
267266 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK ;
268267
269268 switch (reg_subtype ) {
@@ -275,15 +274,16 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
275274 return smstateen_csr_id_to_str (reg_off );
276275 }
277276
278- TEST_FAIL ("%s: Unknown csr subtype: 0x%llx" , prefix , reg_subtype );
279- return NULL ;
277+ return strdup_printf ("%lld | %lld /* UNKNOWN */" , reg_subtype , reg_off );
280278}
281279
282280static const char * timer_id_to_str (const char * prefix , __u64 id )
283281{
284282 /* reg_off is the offset into struct kvm_riscv_timer */
285283 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER );
286284
285+ assert ((id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_TIMER );
286+
287287 switch (reg_off ) {
288288 case KVM_REG_RISCV_TIMER_REG (frequency ):
289289 return "KVM_REG_RISCV_TIMER_REG(frequency)" ;
@@ -295,15 +295,16 @@ static const char *timer_id_to_str(const char *prefix, __u64 id)
295295 return "KVM_REG_RISCV_TIMER_REG(state)" ;
296296 }
297297
298- TEST_FAIL ("%s: Unknown timer reg id: 0x%llx" , prefix , id );
299- return NULL ;
298+ return strdup_printf ("%lld /* UNKNOWN */" , reg_off );
300299}
301300
302301static const char * fp_f_id_to_str (const char * prefix , __u64 id )
303302{
304303 /* reg_off is the offset into struct __riscv_f_ext_state */
305304 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F );
306305
306+ assert ((id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_F );
307+
307308 switch (reg_off ) {
308309 case KVM_REG_RISCV_FP_F_REG (f [0 ]) ...
309310 KVM_REG_RISCV_FP_F_REG (f [31 ]):
@@ -312,15 +313,16 @@ static const char *fp_f_id_to_str(const char *prefix, __u64 id)
312313 return "KVM_REG_RISCV_FP_F_REG(fcsr)" ;
313314 }
314315
315- TEST_FAIL ("%s: Unknown fp_f reg id: 0x%llx" , prefix , id );
316- return NULL ;
316+ return strdup_printf ("%lld /* UNKNOWN */" , reg_off );
317317}
318318
319319static const char * fp_d_id_to_str (const char * prefix , __u64 id )
320320{
321321 /* reg_off is the offset into struct __riscv_d_ext_state */
322322 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D );
323323
324+ assert ((id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_D );
325+
324326 switch (reg_off ) {
325327 case KVM_REG_RISCV_FP_D_REG (f [0 ]) ...
326328 KVM_REG_RISCV_FP_D_REG (f [31 ]):
@@ -329,18 +331,19 @@ static const char *fp_d_id_to_str(const char *prefix, __u64 id)
329331 return "KVM_REG_RISCV_FP_D_REG(fcsr)" ;
330332 }
331333
332- TEST_FAIL ("%s: Unknown fp_d reg id: 0x%llx" , prefix , id );
333- return NULL ;
334+ return strdup_printf ("%lld /* UNKNOWN */" , reg_off );
334335}
335336
336337#define KVM_ISA_EXT_ARR (ext ) \
337338[KVM_RISCV_ISA_EXT_##ext] = "KVM_RISCV_ISA_EXT_" #ext
338339
339- static const char * isa_ext_id_to_str (__u64 id )
340+ static const char * isa_ext_id_to_str (const char * prefix , __u64 id )
340341{
341342 /* reg_off is the offset into unsigned long kvm_isa_ext_arr[] */
342343 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT );
343344
345+ assert ((id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_ISA_EXT );
346+
344347 static const char * const kvm_isa_ext_reg_name [] = {
345348 KVM_ISA_EXT_ARR (A ),
346349 KVM_ISA_EXT_ARR (C ),
@@ -369,13 +372,8 @@ static const char *isa_ext_id_to_str(__u64 id)
369372 KVM_ISA_EXT_ARR (ZIHPM ),
370373 };
371374
372- if (reg_off >= ARRAY_SIZE (kvm_isa_ext_reg_name )) {
373- /*
374- * isa_ext regs would grow regularly with new isa extension added, so
375- * just show "reg" to indicate a new extension.
376- */
375+ if (reg_off >= ARRAY_SIZE (kvm_isa_ext_reg_name ))
377376 return strdup_printf ("%lld /* UNKNOWN */" , reg_off );
378- }
379377
380378 return kvm_isa_ext_reg_name [reg_off ];
381379}
@@ -398,42 +396,36 @@ static const char *sbi_ext_single_id_to_str(__u64 reg_off)
398396 KVM_SBI_EXT_ARR (KVM_RISCV_SBI_EXT_VENDOR ),
399397 };
400398
401- if (reg_off >= ARRAY_SIZE (kvm_sbi_ext_reg_name )) {
402- /*
403- * sbi_ext regs would grow regularly with new sbi extension added, so
404- * just show "reg" to indicate a new extension.
405- */
399+ if (reg_off >= ARRAY_SIZE (kvm_sbi_ext_reg_name ))
406400 return strdup_printf ("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */" , reg_off );
407- }
408401
409402 return kvm_sbi_ext_reg_name [reg_off ];
410403}
411404
412405static const char * sbi_ext_multi_id_to_str (__u64 reg_subtype , __u64 reg_off )
413406{
414- if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST ) {
415- /*
416- * sbi_ext regs would grow regularly with new sbi extension added, so
417- * just show "reg" to indicate a new extension.
418- */
419- return strdup_printf ("%lld /* UNKNOWN */" , reg_off );
420- }
407+ const char * unknown = "" ;
408+
409+ if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST )
410+ unknown = " /* UNKNOWN */" ;
421411
422412 switch (reg_subtype ) {
423413 case KVM_REG_RISCV_SBI_MULTI_EN :
424- return strdup_printf ("KVM_REG_RISCV_SBI_MULTI_EN | %lld" , reg_off );
414+ return strdup_printf ("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s " , reg_off , unknown );
425415 case KVM_REG_RISCV_SBI_MULTI_DIS :
426- return strdup_printf ("KVM_REG_RISCV_SBI_MULTI_DIS | %lld" , reg_off );
416+ return strdup_printf ("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s " , reg_off , unknown );
427417 }
428418
429- return NULL ;
419+ return strdup_printf ( "%lld | %lld /* UNKNOWN */" , reg_subtype , reg_off ) ;
430420}
431421
432422static const char * sbi_ext_id_to_str (const char * prefix , __u64 id )
433423{
434424 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT );
435425 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK ;
436426
427+ assert ((id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_SBI_EXT );
428+
437429 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK ;
438430
439431 switch (reg_subtype ) {
@@ -444,8 +436,7 @@ static const char *sbi_ext_id_to_str(const char *prefix, __u64 id)
444436 return sbi_ext_multi_id_to_str (reg_subtype , reg_off );
445437 }
446438
447- TEST_FAIL ("%s: Unknown sbi ext subtype: 0x%llx" , prefix , reg_subtype );
448- return NULL ;
439+ return strdup_printf ("%lld | %lld /* UNKNOWN */" , reg_subtype , reg_off );
449440}
450441
451442void print_reg (const char * prefix , __u64 id )
@@ -466,14 +457,14 @@ void print_reg(const char *prefix, __u64 id)
466457 reg_size = "KVM_REG_SIZE_U128" ;
467458 break ;
468459 default :
469- TEST_FAIL ( "%s: Unexpected reg size: 0x%llx in reg id: 0x%llx " ,
470- prefix , (id & KVM_REG_SIZE_MASK ) >> KVM_REG_SIZE_SHIFT , id );
460+ printf ( "\tKVM_REG_RISCV | (%lld << KVM_REG_SIZE_SHIFT) | 0x%llx /* UNKNOWN */, " ,
461+ (id & KVM_REG_SIZE_MASK ) >> KVM_REG_SIZE_SHIFT , id & REG_MASK );
471462 }
472463
473464 switch (id & KVM_REG_RISCV_TYPE_MASK ) {
474465 case KVM_REG_RISCV_CONFIG :
475466 printf ("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n" ,
476- reg_size , config_id_to_str (id ));
467+ reg_size , config_id_to_str (prefix , id ));
477468 break ;
478469 case KVM_REG_RISCV_CORE :
479470 printf ("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n" ,
@@ -497,15 +488,15 @@ void print_reg(const char *prefix, __u64 id)
497488 break ;
498489 case KVM_REG_RISCV_ISA_EXT :
499490 printf ("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n" ,
500- reg_size , isa_ext_id_to_str (id ));
491+ reg_size , isa_ext_id_to_str (prefix , id ));
501492 break ;
502493 case KVM_REG_RISCV_SBI_EXT :
503494 printf ("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n" ,
504495 reg_size , sbi_ext_id_to_str (prefix , id ));
505496 break ;
506497 default :
507- TEST_FAIL ( "%s: Unexpected reg type: 0x%llx in reg id: 0x%llx" , prefix ,
508- ( id & KVM_REG_RISCV_TYPE_MASK ) >> KVM_REG_RISCV_TYPE_SHIFT , id );
498+ printf ( "\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */," ,
499+ reg_size , id & REG_MASK );
509500 }
510501}
511502
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