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torvaldstorvalds
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Merge tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: - fix for loongson64 device tree - add SPI nand to realtek device tree - change clock tree for mobileye * tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a mips: dts: realtek: Add SPI NAND controller MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks
2 parents 9d5daef + 4fbd66d commit 63c81af

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-345
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6 files changed

+166
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‎arch/mips/boot/dts/loongson/ls7a-pch.dtsi‎

Lines changed: 60 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,6 @@
7070
device_type = "pci";
7171
#address-cells = <3>;
7272
#size-cells = <2>;
73-
#interrupt-cells = <2>;
7473
msi-parent = <&msi>;
7574

7675
reg = <0 0x1a000000 0 0x02000000>,
@@ -234,7 +233,7 @@
234233
};
235234
};
236235

237-
pci_bridge@9,0 {
236+
pcie@9,0 {
238237
compatible = "pci0014,7a19.1",
239238
"pci0014,7a19",
240239
"pciclass060400",
@@ -244,12 +243,16 @@
244243
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
245244
interrupt-parent = <&pic>;
246245

246+
#address-cells = <3>;
247+
#size-cells = <2>;
248+
device_type = "pci";
247249
#interrupt-cells = <1>;
248250
interrupt-map-mask = <0 0 0 0>;
249251
interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
252+
ranges;
250253
};
251254

252-
pci_bridge@a,0 {
255+
pcie@a,0 {
253256
compatible = "pci0014,7a09.1",
254257
"pci0014,7a09",
255258
"pciclass060400",
@@ -259,12 +262,16 @@
259262
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
260263
interrupt-parent = <&pic>;
261264

265+
#address-cells = <3>;
266+
#size-cells = <2>;
267+
device_type = "pci";
262268
#interrupt-cells = <1>;
263269
interrupt-map-mask = <0 0 0 0>;
264270
interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
271+
ranges;
265272
};
266273

267-
pci_bridge@b,0 {
274+
pcie@b,0 {
268275
compatible = "pci0014,7a09.1",
269276
"pci0014,7a09",
270277
"pciclass060400",
@@ -274,12 +281,16 @@
274281
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
275282
interrupt-parent = <&pic>;
276283

284+
#address-cells = <3>;
285+
#size-cells = <2>;
286+
device_type = "pci";
277287
#interrupt-cells = <1>;
278288
interrupt-map-mask = <0 0 0 0>;
279289
interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
290+
ranges;
280291
};
281292

282-
pci_bridge@c,0 {
293+
pcie@c,0 {
283294
compatible = "pci0014,7a09.1",
284295
"pci0014,7a09",
285296
"pciclass060400",
@@ -289,12 +300,16 @@
289300
interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
290301
interrupt-parent = <&pic>;
291302

303+
#address-cells = <3>;
304+
#size-cells = <2>;
305+
device_type = "pci";
292306
#interrupt-cells = <1>;
293307
interrupt-map-mask = <0 0 0 0>;
294308
interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
309+
ranges;
295310
};
296311

297-
pci_bridge@d,0 {
312+
pcie@d,0 {
298313
compatible = "pci0014,7a19.1",
299314
"pci0014,7a19",
300315
"pciclass060400",
@@ -304,12 +319,16 @@
304319
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
305320
interrupt-parent = <&pic>;
306321

322+
#address-cells = <3>;
323+
#size-cells = <2>;
324+
device_type = "pci";
307325
#interrupt-cells = <1>;
308326
interrupt-map-mask = <0 0 0 0>;
309327
interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
328+
ranges;
310329
};
311330

312-
pci_bridge@e,0 {
331+
pcie@e,0 {
313332
compatible = "pci0014,7a09.1",
314333
"pci0014,7a09",
315334
"pciclass060400",
@@ -319,12 +338,16 @@
319338
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
320339
interrupt-parent = <&pic>;
321340

341+
#address-cells = <3>;
342+
#size-cells = <2>;
343+
device_type = "pci";
322344
#interrupt-cells = <1>;
323345
interrupt-map-mask = <0 0 0 0>;
324346
interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
347+
ranges;
325348
};
326349

327-
pci_bridge@f,0 {
350+
pcie@f,0 {
328351
compatible = "pci0014,7a29.1",
329352
"pci0014,7a29",
330353
"pciclass060400",
@@ -334,12 +357,16 @@
334357
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
335358
interrupt-parent = <&pic>;
336359

360+
#address-cells = <3>;
361+
#size-cells = <2>;
362+
device_type = "pci";
337363
#interrupt-cells = <1>;
338364
interrupt-map-mask = <0 0 0 0>;
339365
interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
366+
ranges;
340367
};
341368

342-
pci_bridge@10,0 {
369+
pcie@10,0 {
343370
compatible = "pci0014,7a19.1",
344371
"pci0014,7a19",
345372
"pciclass060400",
@@ -349,12 +376,16 @@
349376
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
350377
interrupt-parent = <&pic>;
351378

379+
#address-cells = <3>;
380+
#size-cells = <2>;
381+
device_type = "pci";
352382
#interrupt-cells = <1>;
353383
interrupt-map-mask = <0 0 0 0>;
354384
interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
385+
ranges;
355386
};
356387

357-
pci_bridge@11,0 {
388+
pcie@11,0 {
358389
compatible = "pci0014,7a29.1",
359390
"pci0014,7a29",
360391
"pciclass060400",
@@ -364,12 +395,16 @@
364395
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
365396
interrupt-parent = <&pic>;
366397

398+
#address-cells = <3>;
399+
#size-cells = <2>;
400+
device_type = "pci";
367401
#interrupt-cells = <1>;
368402
interrupt-map-mask = <0 0 0 0>;
369403
interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
404+
ranges;
370405
};
371406

372-
pci_bridge@12,0 {
407+
pcie@12,0 {
373408
compatible = "pci0014,7a19.1",
374409
"pci0014,7a19",
375410
"pciclass060400",
@@ -379,12 +414,16 @@
379414
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
380415
interrupt-parent = <&pic>;
381416

417+
#address-cells = <3>;
418+
#size-cells = <2>;
419+
device_type = "pci";
382420
#interrupt-cells = <1>;
383421
interrupt-map-mask = <0 0 0 0>;
384422
interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
423+
ranges;
385424
};
386425

387-
pci_bridge@13,0 {
426+
pcie@13,0 {
388427
compatible = "pci0014,7a29.1",
389428
"pci0014,7a29",
390429
"pciclass060400",
@@ -394,12 +433,16 @@
394433
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
395434
interrupt-parent = <&pic>;
396435

436+
#address-cells = <3>;
437+
#size-cells = <2>;
438+
device_type = "pci";
397439
#interrupt-cells = <1>;
398440
interrupt-map-mask = <0 0 0 0>;
399441
interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
442+
ranges;
400443
};
401444

402-
pci_bridge@14,0 {
445+
pcie@14,0 {
403446
compatible = "pci0014,7a19.1",
404447
"pci0014,7a19",
405448
"pciclass060400",
@@ -409,9 +452,13 @@
409452
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
410453
interrupt-parent = <&pic>;
411454

455+
#address-cells = <3>;
456+
#size-cells = <2>;
457+
device_type = "pci";
412458
#interrupt-cells = <1>;
413459
interrupt-map-mask = <0 0 0 0>;
414460
interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
461+
ranges;
415462
};
416463
};
417464

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