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Merge branches 'clk-stm', 'clk-renesas', 'clk-scmi' and 'clk-allwinner' into clk-next
 - STM32MP257 SoC clk driver - Allocate clk_ops dynamically for SCMI clk driver * clk-stm: dt-bindings: clocks: stm32mp25: add access-controllers description clk: stm32: introduce clocks for STM32MP257 platform dt-bindings: clocks: stm32mp25: add description of all parents clk: stm32mp13: use platform device APIs * clk-renesas: clk: renesas: r9a08g045: Add support for power domains clk: renesas: rzg2l: Extend power domain support dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S dt-bindings: clock: r9a08g045-cpg: Add power domain IDs dt-bindings: clock: r9a07g054-cpg: Add power domain IDs dt-bindings: clock: r9a07g044-cpg: Add power domain IDs dt-bindings: clock: r9a07g043-cpg: Add power domain IDs clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT clk: renesas: r8a7740: Remove unused div4_clk.flags field clk: renesas: r9a07g043: Add clock and reset entry for PLIC clk: renesas: r8a779h0: Add INTC-EX clock clk: renesas: r8a779h0: Add MSIOF clocks clk: renesas: r8a779a0: Fix CANFD parent clock clk: rs9: fix wrong default value for clock amplitude clk: renesas: r8a779h0: Add timer clocks clk: renesas: r8a779h0: Add SCIF clocks clk: renesas: r9a07g044: Mark resets array as const clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const clk: renesas: r8a779h0: Add thermal clock dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks * clk-scmi: clk: scmi: Add support for get/set duty_cycle operations clk: scmi: Add support for re-parenting restricted clocks clk: scmi: Add support for rate change restricted clocks clk: scmi: Add support for state control restricted clocks clk: scmi: Allocate CLK operations dynamically * clk-allwinner: clk: sunxi-ng: fix module autoloading clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
5 parents 5aabfd9 + 12b52b8 + 8beff78 + 87af948 + 19149b3 commit 7552d1b

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‎Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,8 @@ properties:
5757
can be power-managed through Module Standby should refer to the CPG device
5858
node in their "power-domains" property, as documented by the generic PM
5959
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
60-
const: 0
60+
The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
61+
be used to reference individual CPG power domains.
6162

6263
'#reset-cells':
6364
description:
@@ -76,6 +77,21 @@ required:
7677

7778
additionalProperties: false
7879

80+
allOf:
81+
- if:
82+
properties:
83+
compatible:
84+
contains:
85+
const: renesas,r9a08g045-cpg
86+
then:
87+
properties:
88+
'#power-domain-cells':
89+
const: 1
90+
else:
91+
properties:
92+
'#power-domain-cells':
93+
const: 0
94+
7995
examples:
8096
- |
8197
cpg: clock-controller@11010000 {

‎Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml‎

Lines changed: 158 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -38,22 +38,92 @@ properties:
3838
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
3939
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
4040
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
41+
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
42+
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
43+
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
44+
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
45+
- description: CK_SCMI_ICN_DDR DDR interconnect bus clock
46+
- description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
47+
- description: CK_SCMI_ICN_HSL HSL interconnect bus clock
48+
- description: CK_SCMI_ICN_NIC NIC interconnect bus clock
49+
- description: CK_SCMI_ICN_VID Video interconnect bus clock
50+
- description: CK_SCMI_FLEXGEN_07 flexgen clock 7
51+
- description: CK_SCMI_FLEXGEN_08 flexgen clock 8
52+
- description: CK_SCMI_FLEXGEN_09 flexgen clock 9
53+
- description: CK_SCMI_FLEXGEN_10 flexgen clock 10
54+
- description: CK_SCMI_FLEXGEN_11 flexgen clock 11
55+
- description: CK_SCMI_FLEXGEN_12 flexgen clock 12
56+
- description: CK_SCMI_FLEXGEN_13 flexgen clock 13
57+
- description: CK_SCMI_FLEXGEN_14 flexgen clock 14
58+
- description: CK_SCMI_FLEXGEN_15 flexgen clock 15
59+
- description: CK_SCMI_FLEXGEN_16 flexgen clock 16
60+
- description: CK_SCMI_FLEXGEN_17 flexgen clock 17
61+
- description: CK_SCMI_FLEXGEN_18 flexgen clock 18
62+
- description: CK_SCMI_FLEXGEN_19 flexgen clock 19
63+
- description: CK_SCMI_FLEXGEN_20 flexgen clock 20
64+
- description: CK_SCMI_FLEXGEN_21 flexgen clock 21
65+
- description: CK_SCMI_FLEXGEN_22 flexgen clock 22
66+
- description: CK_SCMI_FLEXGEN_23 flexgen clock 23
67+
- description: CK_SCMI_FLEXGEN_24 flexgen clock 24
68+
- description: CK_SCMI_FLEXGEN_25 flexgen clock 25
69+
- description: CK_SCMI_FLEXGEN_26 flexgen clock 26
70+
- description: CK_SCMI_FLEXGEN_27 flexgen clock 27
71+
- description: CK_SCMI_FLEXGEN_28 flexgen clock 28
72+
- description: CK_SCMI_FLEXGEN_29 flexgen clock 29
73+
- description: CK_SCMI_FLEXGEN_30 flexgen clock 30
74+
- description: CK_SCMI_FLEXGEN_31 flexgen clock 31
75+
- description: CK_SCMI_FLEXGEN_32 flexgen clock 32
76+
- description: CK_SCMI_FLEXGEN_33 flexgen clock 33
77+
- description: CK_SCMI_FLEXGEN_34 flexgen clock 34
78+
- description: CK_SCMI_FLEXGEN_35 flexgen clock 35
79+
- description: CK_SCMI_FLEXGEN_36 flexgen clock 36
80+
- description: CK_SCMI_FLEXGEN_37 flexgen clock 37
81+
- description: CK_SCMI_FLEXGEN_38 flexgen clock 38
82+
- description: CK_SCMI_FLEXGEN_39 flexgen clock 39
83+
- description: CK_SCMI_FLEXGEN_40 flexgen clock 40
84+
- description: CK_SCMI_FLEXGEN_41 flexgen clock 41
85+
- description: CK_SCMI_FLEXGEN_42 flexgen clock 42
86+
- description: CK_SCMI_FLEXGEN_43 flexgen clock 43
87+
- description: CK_SCMI_FLEXGEN_44 flexgen clock 44
88+
- description: CK_SCMI_FLEXGEN_45 flexgen clock 45
89+
- description: CK_SCMI_FLEXGEN_46 flexgen clock 46
90+
- description: CK_SCMI_FLEXGEN_47 flexgen clock 47
91+
- description: CK_SCMI_FLEXGEN_48 flexgen clock 48
92+
- description: CK_SCMI_FLEXGEN_49 flexgen clock 49
93+
- description: CK_SCMI_FLEXGEN_50 flexgen clock 50
94+
- description: CK_SCMI_FLEXGEN_51 flexgen clock 51
95+
- description: CK_SCMI_FLEXGEN_52 flexgen clock 52
96+
- description: CK_SCMI_FLEXGEN_53 flexgen clock 53
97+
- description: CK_SCMI_FLEXGEN_54 flexgen clock 54
98+
- description: CK_SCMI_FLEXGEN_55 flexgen clock 55
99+
- description: CK_SCMI_FLEXGEN_56 flexgen clock 56
100+
- description: CK_SCMI_FLEXGEN_57 flexgen clock 57
101+
- description: CK_SCMI_FLEXGEN_58 flexgen clock 58
102+
- description: CK_SCMI_FLEXGEN_59 flexgen clock 59
103+
- description: CK_SCMI_FLEXGEN_60 flexgen clock 60
104+
- description: CK_SCMI_FLEXGEN_61 flexgen clock 61
105+
- description: CK_SCMI_FLEXGEN_62 flexgen clock 62
106+
- description: CK_SCMI_FLEXGEN_63 flexgen clock 63
107+
- description: CK_SCMI_ICN_APB1 Peripheral bridge 1
108+
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
109+
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
110+
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
111+
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
112+
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
113+
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
114+
- description: CK_SCMI_PLL3 PLL3 clock
115+
- description: clk_dsi_txbyte DSI byte clock
41116

42-
clock-names:
43-
items:
44-
- const: hse
45-
- const: hsi
46-
- const: msi
47-
- const: lse
48-
- const: lsi
117+
access-controllers:
118+
minItems: 1
119+
maxItems: 2
49120

50121
required:
51122
- compatible
52123
- reg
53124
- '#clock-cells'
54125
- '#reset-cells'
55126
- clocks
56-
- clock-names
57127

58128
additionalProperties: false
59129

@@ -66,11 +136,85 @@ examples:
66136
reg = <0x44200000 0x10000>;
67137
#clock-cells = <1>;
68138
#reset-cells = <1>;
69-
clock-names = "hse", "hsi", "msi", "lse", "lsi";
70-
clocks = <&scmi_clk CK_SCMI_HSE>,
71-
<&scmi_clk CK_SCMI_HSI>,
72-
<&scmi_clk CK_SCMI_MSI>,
73-
<&scmi_clk CK_SCMI_LSE>,
74-
<&scmi_clk CK_SCMI_LSI>;
139+
clocks = <&scmi_clk CK_SCMI_HSE>,
140+
<&scmi_clk CK_SCMI_HSI>,
141+
<&scmi_clk CK_SCMI_MSI>,
142+
<&scmi_clk CK_SCMI_LSE>,
143+
<&scmi_clk CK_SCMI_LSI>,
144+
<&scmi_clk CK_SCMI_HSE_DIV2>,
145+
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
146+
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
147+
<&scmi_clk CK_SCMI_ICN_SDMMC>,
148+
<&scmi_clk CK_SCMI_ICN_DDR>,
149+
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
150+
<&scmi_clk CK_SCMI_ICN_HSL>,
151+
<&scmi_clk CK_SCMI_ICN_NIC>,
152+
<&scmi_clk CK_SCMI_ICN_VID>,
153+
<&scmi_clk CK_SCMI_FLEXGEN_07>,
154+
<&scmi_clk CK_SCMI_FLEXGEN_08>,
155+
<&scmi_clk CK_SCMI_FLEXGEN_09>,
156+
<&scmi_clk CK_SCMI_FLEXGEN_10>,
157+
<&scmi_clk CK_SCMI_FLEXGEN_11>,
158+
<&scmi_clk CK_SCMI_FLEXGEN_12>,
159+
<&scmi_clk CK_SCMI_FLEXGEN_13>,
160+
<&scmi_clk CK_SCMI_FLEXGEN_14>,
161+
<&scmi_clk CK_SCMI_FLEXGEN_15>,
162+
<&scmi_clk CK_SCMI_FLEXGEN_16>,
163+
<&scmi_clk CK_SCMI_FLEXGEN_17>,
164+
<&scmi_clk CK_SCMI_FLEXGEN_18>,
165+
<&scmi_clk CK_SCMI_FLEXGEN_19>,
166+
<&scmi_clk CK_SCMI_FLEXGEN_20>,
167+
<&scmi_clk CK_SCMI_FLEXGEN_21>,
168+
<&scmi_clk CK_SCMI_FLEXGEN_22>,
169+
<&scmi_clk CK_SCMI_FLEXGEN_23>,
170+
<&scmi_clk CK_SCMI_FLEXGEN_24>,
171+
<&scmi_clk CK_SCMI_FLEXGEN_25>,
172+
<&scmi_clk CK_SCMI_FLEXGEN_26>,
173+
<&scmi_clk CK_SCMI_FLEXGEN_27>,
174+
<&scmi_clk CK_SCMI_FLEXGEN_28>,
175+
<&scmi_clk CK_SCMI_FLEXGEN_29>,
176+
<&scmi_clk CK_SCMI_FLEXGEN_30>,
177+
<&scmi_clk CK_SCMI_FLEXGEN_31>,
178+
<&scmi_clk CK_SCMI_FLEXGEN_32>,
179+
<&scmi_clk CK_SCMI_FLEXGEN_33>,
180+
<&scmi_clk CK_SCMI_FLEXGEN_34>,
181+
<&scmi_clk CK_SCMI_FLEXGEN_35>,
182+
<&scmi_clk CK_SCMI_FLEXGEN_36>,
183+
<&scmi_clk CK_SCMI_FLEXGEN_37>,
184+
<&scmi_clk CK_SCMI_FLEXGEN_38>,
185+
<&scmi_clk CK_SCMI_FLEXGEN_39>,
186+
<&scmi_clk CK_SCMI_FLEXGEN_40>,
187+
<&scmi_clk CK_SCMI_FLEXGEN_41>,
188+
<&scmi_clk CK_SCMI_FLEXGEN_42>,
189+
<&scmi_clk CK_SCMI_FLEXGEN_43>,
190+
<&scmi_clk CK_SCMI_FLEXGEN_44>,
191+
<&scmi_clk CK_SCMI_FLEXGEN_45>,
192+
<&scmi_clk CK_SCMI_FLEXGEN_46>,
193+
<&scmi_clk CK_SCMI_FLEXGEN_47>,
194+
<&scmi_clk CK_SCMI_FLEXGEN_48>,
195+
<&scmi_clk CK_SCMI_FLEXGEN_49>,
196+
<&scmi_clk CK_SCMI_FLEXGEN_50>,
197+
<&scmi_clk CK_SCMI_FLEXGEN_51>,
198+
<&scmi_clk CK_SCMI_FLEXGEN_52>,
199+
<&scmi_clk CK_SCMI_FLEXGEN_53>,
200+
<&scmi_clk CK_SCMI_FLEXGEN_54>,
201+
<&scmi_clk CK_SCMI_FLEXGEN_55>,
202+
<&scmi_clk CK_SCMI_FLEXGEN_56>,
203+
<&scmi_clk CK_SCMI_FLEXGEN_57>,
204+
<&scmi_clk CK_SCMI_FLEXGEN_58>,
205+
<&scmi_clk CK_SCMI_FLEXGEN_59>,
206+
<&scmi_clk CK_SCMI_FLEXGEN_60>,
207+
<&scmi_clk CK_SCMI_FLEXGEN_61>,
208+
<&scmi_clk CK_SCMI_FLEXGEN_62>,
209+
<&scmi_clk CK_SCMI_FLEXGEN_63>,
210+
<&scmi_clk CK_SCMI_ICN_APB1>,
211+
<&scmi_clk CK_SCMI_ICN_APB2>,
212+
<&scmi_clk CK_SCMI_ICN_APB3>,
213+
<&scmi_clk CK_SCMI_ICN_APB4>,
214+
<&scmi_clk CK_SCMI_ICN_APBDBG>,
215+
<&scmi_clk CK_SCMI_TIMG1>,
216+
<&scmi_clk CK_SCMI_TIMG2>,
217+
<&scmi_clk CK_SCMI_PLL3>,
218+
<&clk_dsi_txbyte>;
75219
};
76220
...

‎drivers/clk/clk-renesas-pcie.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,10 +25,12 @@
2525
#define RS9_REG_SS_AMP_0V7 0x1
2626
#define RS9_REG_SS_AMP_0V8 0x2
2727
#define RS9_REG_SS_AMP_0V9 0x3
28+
#define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8
2829
#define RS9_REG_SS_AMP_MASK 0x3
2930
#define RS9_REG_SS_SSC_100 0
3031
#define RS9_REG_SS_SSC_M025 (1 << 3)
3132
#define RS9_REG_SS_SSC_M050 (3 << 3)
33+
#define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100
3234
#define RS9_REG_SS_SSC_MASK (3 << 3)
3335
#define RS9_REG_SS_SSC_LOCK BIT(5)
3436
#define RS9_REG_SR 0x2
@@ -205,8 +207,8 @@ static int rs9_get_common_config(struct rs9_driver_data *rs9)
205207
int ret;
206208

207209
/* Set defaults */
208-
rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
209-
rs9->pll_ssc = RS9_REG_SS_SSC_100;
210+
rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT;
211+
rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT;
210212

211213
/* Output clock amplitude */
212214
ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt",
@@ -247,13 +249,13 @@ static void rs9_update_config(struct rs9_driver_data *rs9)
247249
int i;
248250

249251
/* If amplitude is non-default, update it. */
250-
if (rs9->pll_amplitude != RS9_REG_SS_AMP_0V7) {
252+
if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) {
251253
regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK,
252254
rs9->pll_amplitude);
253255
}
254256

255257
/* If SSC is non-default, update it. */
256-
if (rs9->pll_ssc != RS9_REG_SS_SSC_100) {
258+
if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) {
257259
regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK,
258260
rs9->pll_ssc);
259261
}

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