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Sheetalbroonie
Sheetal
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broonie
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ASoC: tegra: ADMAIF: Add Tegra264 support
Add Tegra264 I2S support with following changes: - Add soc_data for Tegra264-specific variations - Tegra264 supports 32 RX and 32 TX ADMAIF channels and each ADMAIF stream supports max 32 channels. To accommodate the change dais, CIF configuration API and driver components are updated. - Register offsets and default values are updated to align with Tegra264. Signed-off-by: Sheetal <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Mark Brown <[email protected]>
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‎sound/soc/tegra/tegra210_admaif.c‎

Lines changed: 185 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -25,20 +25,21 @@
2525

2626
#define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id)
2727

28-
#define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base, rx_base) \
28+
#define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base, rx_base, cif_ctrl) \
2929
{ CH_REG(rx_base, TEGRA_ADMAIF_RX_INT_MASK, id), 0x00000001 }, \
30-
{ CH_REG(rx_base, TEGRA_ADMAIF_CH_ACIF_RX_CTRL, id), 0x00007700 }, \
30+
{ CH_REG(rx_base, TEGRA_ADMAIF_CH_ACIF_RX_CTRL, id), cif_ctrl }, \
3131
{ CH_REG(rx_base, TEGRA_ADMAIF_RX_FIFO_CTRL, id), rx_ctrl }, \
3232
{ CH_REG(tx_base, TEGRA_ADMAIF_TX_INT_MASK, id), 0x00000001 }, \
33-
{ CH_REG(tx_base, TEGRA_ADMAIF_CH_ACIF_TX_CTRL, id), 0x00007700 }, \
33+
{ CH_REG(tx_base, TEGRA_ADMAIF_CH_ACIF_TX_CTRL, id), cif_ctrl }, \
3434
{ CH_REG(tx_base, TEGRA_ADMAIF_TX_FIFO_CTRL, id), tx_ctrl }
3535

3636
#define ADMAIF_REG_DEFAULTS(id, chip) \
3737
REG_DEFAULTS((id) - 1, \
3838
chip ## _ADMAIF_RX ## id ## _FIFO_CTRL_REG_DEFAULT, \
3939
chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT, \
4040
chip ## _ADMAIF_TX_BASE, \
41-
chip ## _ADMAIF_RX_BASE)
41+
chip ## _ADMAIF_RX_BASE, \
42+
chip ## _ADMAIF_CIF_REG_DEFAULT)
4243

4344
static const struct reg_default tegra186_admaif_reg_defaults[] = {
4445
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003},
@@ -78,6 +79,42 @@ static const struct reg_default tegra210_admaif_reg_defaults[] = {
7879
ADMAIF_REG_DEFAULTS(10, TEGRA210)
7980
};
8081

82+
static const struct reg_default tegra264_admaif_reg_defaults[] = {
83+
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA264_ADMAIF_GLOBAL_BASE), 0x00000003},
84+
ADMAIF_REG_DEFAULTS(1, TEGRA264),
85+
ADMAIF_REG_DEFAULTS(2, TEGRA264),
86+
ADMAIF_REG_DEFAULTS(3, TEGRA264),
87+
ADMAIF_REG_DEFAULTS(4, TEGRA264),
88+
ADMAIF_REG_DEFAULTS(5, TEGRA264),
89+
ADMAIF_REG_DEFAULTS(6, TEGRA264),
90+
ADMAIF_REG_DEFAULTS(7, TEGRA264),
91+
ADMAIF_REG_DEFAULTS(8, TEGRA264),
92+
ADMAIF_REG_DEFAULTS(9, TEGRA264),
93+
ADMAIF_REG_DEFAULTS(10, TEGRA264),
94+
ADMAIF_REG_DEFAULTS(11, TEGRA264),
95+
ADMAIF_REG_DEFAULTS(12, TEGRA264),
96+
ADMAIF_REG_DEFAULTS(13, TEGRA264),
97+
ADMAIF_REG_DEFAULTS(14, TEGRA264),
98+
ADMAIF_REG_DEFAULTS(15, TEGRA264),
99+
ADMAIF_REG_DEFAULTS(16, TEGRA264),
100+
ADMAIF_REG_DEFAULTS(17, TEGRA264),
101+
ADMAIF_REG_DEFAULTS(18, TEGRA264),
102+
ADMAIF_REG_DEFAULTS(19, TEGRA264),
103+
ADMAIF_REG_DEFAULTS(20, TEGRA264),
104+
ADMAIF_REG_DEFAULTS(21, TEGRA264),
105+
ADMAIF_REG_DEFAULTS(22, TEGRA264),
106+
ADMAIF_REG_DEFAULTS(23, TEGRA264),
107+
ADMAIF_REG_DEFAULTS(24, TEGRA264),
108+
ADMAIF_REG_DEFAULTS(25, TEGRA264),
109+
ADMAIF_REG_DEFAULTS(26, TEGRA264),
110+
ADMAIF_REG_DEFAULTS(27, TEGRA264),
111+
ADMAIF_REG_DEFAULTS(28, TEGRA264),
112+
ADMAIF_REG_DEFAULTS(29, TEGRA264),
113+
ADMAIF_REG_DEFAULTS(30, TEGRA264),
114+
ADMAIF_REG_DEFAULTS(31, TEGRA264),
115+
ADMAIF_REG_DEFAULTS(32, TEGRA264)
116+
};
117+
81118
static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)
82119
{
83120
struct tegra_admaif *admaif = dev_get_drvdata(dev);
@@ -220,6 +257,19 @@ static const struct regmap_config tegra186_admaif_regmap_config = {
220257
.cache_type = REGCACHE_FLAT,
221258
};
222259

260+
static const struct regmap_config tegra264_admaif_regmap_config = {
261+
.reg_bits = 32,
262+
.reg_stride = 4,
263+
.val_bits = 32,
264+
.max_register = TEGRA264_ADMAIF_LAST_REG,
265+
.writeable_reg = tegra_admaif_wr_reg,
266+
.readable_reg = tegra_admaif_rd_reg,
267+
.volatile_reg = tegra_admaif_volatile_reg,
268+
.reg_defaults = tegra264_admaif_reg_defaults,
269+
.num_reg_defaults = TEGRA264_ADMAIF_CHANNEL_COUNT * 6 + 1,
270+
.cache_type = REGCACHE_FLAT,
271+
};
272+
223273
static int tegra_admaif_runtime_suspend(struct device *dev)
224274
{
225275
struct tegra_admaif *admaif = dev_get_drvdata(dev);
@@ -330,7 +380,10 @@ static int tegra_admaif_hw_params(struct snd_pcm_substream *substream,
330380

331381
tegra_admaif_set_pack_mode(admaif->regmap, reg, valid_bit);
332382

333-
tegra_set_cif(admaif->regmap, reg, &cif_conf);
383+
if (admaif->soc_data->max_stream_ch == TEGRA264_ADMAIF_MAX_CHANNEL)
384+
tegra264_set_cif(admaif->regmap, reg, &cif_conf);
385+
else
386+
tegra_set_cif(admaif->regmap, reg, &cif_conf);
334387

335388
return 0;
336389
}
@@ -571,13 +624,13 @@ static const struct snd_soc_dai_ops tegra_admaif_dai_ops = {
571624
.prepare = tegra_admaif_prepare,
572625
};
573626

574-
#define DAI(dai_name) \
627+
#define DAI(dai_name, channel) \
575628
{ \
576629
.name = dai_name, \
577630
.playback = { \
578631
.stream_name = dai_name " Playback", \
579632
.channels_min = 1, \
580-
.channels_max = 16, \
633+
.channels_max = channel, \
581634
.rates = SNDRV_PCM_RATE_8000_192000, \
582635
.formats = SNDRV_PCM_FMTBIT_S8 | \
583636
SNDRV_PCM_FMTBIT_S16_LE | \
@@ -587,7 +640,7 @@ static const struct snd_soc_dai_ops tegra_admaif_dai_ops = {
587640
.capture = { \
588641
.stream_name = dai_name " Capture", \
589642
.channels_min = 1, \
590-
.channels_max = 16, \
643+
.channels_max = channel, \
591644
.rates = SNDRV_PCM_RATE_8000_192000, \
592645
.formats = SNDRV_PCM_FMTBIT_S8 | \
593646
SNDRV_PCM_FMTBIT_S16_LE | \
@@ -598,39 +651,74 @@ static const struct snd_soc_dai_ops tegra_admaif_dai_ops = {
598651
}
599652

600653
static struct snd_soc_dai_driver tegra210_admaif_cmpnt_dais[] = {
601-
DAI("ADMAIF1"),
602-
DAI("ADMAIF2"),
603-
DAI("ADMAIF3"),
604-
DAI("ADMAIF4"),
605-
DAI("ADMAIF5"),
606-
DAI("ADMAIF6"),
607-
DAI("ADMAIF7"),
608-
DAI("ADMAIF8"),
609-
DAI("ADMAIF9"),
610-
DAI("ADMAIF10"),
654+
DAI("ADMAIF1", TEGRA210_ADMAIF_MAX_CHANNEL),
655+
DAI("ADMAIF2", TEGRA210_ADMAIF_MAX_CHANNEL),
656+
DAI("ADMAIF3", TEGRA210_ADMAIF_MAX_CHANNEL),
657+
DAI("ADMAIF4", TEGRA210_ADMAIF_MAX_CHANNEL),
658+
DAI("ADMAIF5", TEGRA210_ADMAIF_MAX_CHANNEL),
659+
DAI("ADMAIF6", TEGRA210_ADMAIF_MAX_CHANNEL),
660+
DAI("ADMAIF7", TEGRA210_ADMAIF_MAX_CHANNEL),
661+
DAI("ADMAIF8", TEGRA210_ADMAIF_MAX_CHANNEL),
662+
DAI("ADMAIF9", TEGRA210_ADMAIF_MAX_CHANNEL),
663+
DAI("ADMAIF10", TEGRA210_ADMAIF_MAX_CHANNEL),
611664
};
612665

613666
static struct snd_soc_dai_driver tegra186_admaif_cmpnt_dais[] = {
614-
DAI("ADMAIF1"),
615-
DAI("ADMAIF2"),
616-
DAI("ADMAIF3"),
617-
DAI("ADMAIF4"),
618-
DAI("ADMAIF5"),
619-
DAI("ADMAIF6"),
620-
DAI("ADMAIF7"),
621-
DAI("ADMAIF8"),
622-
DAI("ADMAIF9"),
623-
DAI("ADMAIF10"),
624-
DAI("ADMAIF11"),
625-
DAI("ADMAIF12"),
626-
DAI("ADMAIF13"),
627-
DAI("ADMAIF14"),
628-
DAI("ADMAIF15"),
629-
DAI("ADMAIF16"),
630-
DAI("ADMAIF17"),
631-
DAI("ADMAIF18"),
632-
DAI("ADMAIF19"),
633-
DAI("ADMAIF20"),
667+
DAI("ADMAIF1", TEGRA186_ADMAIF_MAX_CHANNEL),
668+
DAI("ADMAIF2", TEGRA186_ADMAIF_MAX_CHANNEL),
669+
DAI("ADMAIF3", TEGRA186_ADMAIF_MAX_CHANNEL),
670+
DAI("ADMAIF4", TEGRA186_ADMAIF_MAX_CHANNEL),
671+
DAI("ADMAIF5", TEGRA186_ADMAIF_MAX_CHANNEL),
672+
DAI("ADMAIF6", TEGRA186_ADMAIF_MAX_CHANNEL),
673+
DAI("ADMAIF7", TEGRA186_ADMAIF_MAX_CHANNEL),
674+
DAI("ADMAIF8", TEGRA186_ADMAIF_MAX_CHANNEL),
675+
DAI("ADMAIF9", TEGRA186_ADMAIF_MAX_CHANNEL),
676+
DAI("ADMAIF10", TEGRA186_ADMAIF_MAX_CHANNEL),
677+
DAI("ADMAIF11", TEGRA186_ADMAIF_MAX_CHANNEL),
678+
DAI("ADMAIF12", TEGRA186_ADMAIF_MAX_CHANNEL),
679+
DAI("ADMAIF13", TEGRA186_ADMAIF_MAX_CHANNEL),
680+
DAI("ADMAIF14", TEGRA186_ADMAIF_MAX_CHANNEL),
681+
DAI("ADMAIF15", TEGRA186_ADMAIF_MAX_CHANNEL),
682+
DAI("ADMAIF16", TEGRA186_ADMAIF_MAX_CHANNEL),
683+
DAI("ADMAIF17", TEGRA186_ADMAIF_MAX_CHANNEL),
684+
DAI("ADMAIF18", TEGRA186_ADMAIF_MAX_CHANNEL),
685+
DAI("ADMAIF19", TEGRA186_ADMAIF_MAX_CHANNEL),
686+
DAI("ADMAIF20", TEGRA186_ADMAIF_MAX_CHANNEL),
687+
};
688+
689+
static struct snd_soc_dai_driver tegra264_admaif_cmpnt_dais[] = {
690+
DAI("ADMAIF1", TEGRA264_ADMAIF_MAX_CHANNEL),
691+
DAI("ADMAIF2", TEGRA264_ADMAIF_MAX_CHANNEL),
692+
DAI("ADMAIF3", TEGRA264_ADMAIF_MAX_CHANNEL),
693+
DAI("ADMAIF4", TEGRA264_ADMAIF_MAX_CHANNEL),
694+
DAI("ADMAIF5", TEGRA264_ADMAIF_MAX_CHANNEL),
695+
DAI("ADMAIF6", TEGRA264_ADMAIF_MAX_CHANNEL),
696+
DAI("ADMAIF7", TEGRA264_ADMAIF_MAX_CHANNEL),
697+
DAI("ADMAIF8", TEGRA264_ADMAIF_MAX_CHANNEL),
698+
DAI("ADMAIF9", TEGRA264_ADMAIF_MAX_CHANNEL),
699+
DAI("ADMAIF10", TEGRA264_ADMAIF_MAX_CHANNEL),
700+
DAI("ADMAIF11", TEGRA264_ADMAIF_MAX_CHANNEL),
701+
DAI("ADMAIF12", TEGRA264_ADMAIF_MAX_CHANNEL),
702+
DAI("ADMAIF13", TEGRA264_ADMAIF_MAX_CHANNEL),
703+
DAI("ADMAIF14", TEGRA264_ADMAIF_MAX_CHANNEL),
704+
DAI("ADMAIF15", TEGRA264_ADMAIF_MAX_CHANNEL),
705+
DAI("ADMAIF16", TEGRA264_ADMAIF_MAX_CHANNEL),
706+
DAI("ADMAIF17", TEGRA264_ADMAIF_MAX_CHANNEL),
707+
DAI("ADMAIF18", TEGRA264_ADMAIF_MAX_CHANNEL),
708+
DAI("ADMAIF19", TEGRA264_ADMAIF_MAX_CHANNEL),
709+
DAI("ADMAIF20", TEGRA264_ADMAIF_MAX_CHANNEL),
710+
DAI("ADMAIF21", TEGRA264_ADMAIF_MAX_CHANNEL),
711+
DAI("ADMAIF22", TEGRA264_ADMAIF_MAX_CHANNEL),
712+
DAI("ADMAIF23", TEGRA264_ADMAIF_MAX_CHANNEL),
713+
DAI("ADMAIF24", TEGRA264_ADMAIF_MAX_CHANNEL),
714+
DAI("ADMAIF25", TEGRA264_ADMAIF_MAX_CHANNEL),
715+
DAI("ADMAIF26", TEGRA264_ADMAIF_MAX_CHANNEL),
716+
DAI("ADMAIF27", TEGRA264_ADMAIF_MAX_CHANNEL),
717+
DAI("ADMAIF28", TEGRA264_ADMAIF_MAX_CHANNEL),
718+
DAI("ADMAIF29", TEGRA264_ADMAIF_MAX_CHANNEL),
719+
DAI("ADMAIF30", TEGRA264_ADMAIF_MAX_CHANNEL),
720+
DAI("ADMAIF31", TEGRA264_ADMAIF_MAX_CHANNEL),
721+
DAI("ADMAIF32", TEGRA264_ADMAIF_MAX_CHANNEL),
634722
};
635723

636724
static const char * const tegra_admaif_stereo_conv_text[] = {
@@ -710,6 +798,41 @@ static struct snd_kcontrol_new tegra186_admaif_controls[] = {
710798
TEGRA_ADMAIF_CIF_CTRL(20),
711799
};
712800

801+
static struct snd_kcontrol_new tegra264_admaif_controls[] = {
802+
TEGRA_ADMAIF_CIF_CTRL(1),
803+
TEGRA_ADMAIF_CIF_CTRL(2),
804+
TEGRA_ADMAIF_CIF_CTRL(3),
805+
TEGRA_ADMAIF_CIF_CTRL(4),
806+
TEGRA_ADMAIF_CIF_CTRL(5),
807+
TEGRA_ADMAIF_CIF_CTRL(6),
808+
TEGRA_ADMAIF_CIF_CTRL(7),
809+
TEGRA_ADMAIF_CIF_CTRL(8),
810+
TEGRA_ADMAIF_CIF_CTRL(9),
811+
TEGRA_ADMAIF_CIF_CTRL(10),
812+
TEGRA_ADMAIF_CIF_CTRL(11),
813+
TEGRA_ADMAIF_CIF_CTRL(12),
814+
TEGRA_ADMAIF_CIF_CTRL(13),
815+
TEGRA_ADMAIF_CIF_CTRL(14),
816+
TEGRA_ADMAIF_CIF_CTRL(15),
817+
TEGRA_ADMAIF_CIF_CTRL(16),
818+
TEGRA_ADMAIF_CIF_CTRL(17),
819+
TEGRA_ADMAIF_CIF_CTRL(18),
820+
TEGRA_ADMAIF_CIF_CTRL(19),
821+
TEGRA_ADMAIF_CIF_CTRL(20),
822+
TEGRA_ADMAIF_CIF_CTRL(21),
823+
TEGRA_ADMAIF_CIF_CTRL(22),
824+
TEGRA_ADMAIF_CIF_CTRL(23),
825+
TEGRA_ADMAIF_CIF_CTRL(24),
826+
TEGRA_ADMAIF_CIF_CTRL(25),
827+
TEGRA_ADMAIF_CIF_CTRL(26),
828+
TEGRA_ADMAIF_CIF_CTRL(27),
829+
TEGRA_ADMAIF_CIF_CTRL(28),
830+
TEGRA_ADMAIF_CIF_CTRL(29),
831+
TEGRA_ADMAIF_CIF_CTRL(30),
832+
TEGRA_ADMAIF_CIF_CTRL(31),
833+
TEGRA_ADMAIF_CIF_CTRL(32),
834+
};
835+
713836
static const struct snd_soc_component_driver tegra210_admaif_cmpnt = {
714837
.controls = tegra210_admaif_controls,
715838
.num_controls = ARRAY_SIZE(tegra210_admaif_controls),
@@ -730,8 +853,19 @@ static const struct snd_soc_component_driver tegra186_admaif_cmpnt = {
730853
.pointer = tegra_pcm_pointer,
731854
};
732855

856+
static const struct snd_soc_component_driver tegra264_admaif_cmpnt = {
857+
.controls = tegra264_admaif_controls,
858+
.num_controls = ARRAY_SIZE(tegra264_admaif_controls),
859+
.pcm_construct = tegra_pcm_construct,
860+
.open = tegra_pcm_open,
861+
.close = tegra_pcm_close,
862+
.hw_params = tegra_pcm_hw_params,
863+
.pointer = tegra_pcm_pointer,
864+
};
865+
733866
static const struct tegra_admaif_soc_data soc_data_tegra210 = {
734867
.num_ch = TEGRA210_ADMAIF_CHANNEL_COUNT,
868+
.max_stream_ch = TEGRA210_ADMAIF_MAX_CHANNEL,
735869
.cmpnt = &tegra210_admaif_cmpnt,
736870
.dais = tegra210_admaif_cmpnt_dais,
737871
.regmap_conf = &tegra210_admaif_regmap_config,
@@ -742,6 +876,7 @@ static const struct tegra_admaif_soc_data soc_data_tegra210 = {
742876

743877
static const struct tegra_admaif_soc_data soc_data_tegra186 = {
744878
.num_ch = TEGRA186_ADMAIF_CHANNEL_COUNT,
879+
.max_stream_ch = TEGRA186_ADMAIF_MAX_CHANNEL,
745880
.cmpnt = &tegra186_admaif_cmpnt,
746881
.dais = tegra186_admaif_cmpnt_dais,
747882
.regmap_conf = &tegra186_admaif_regmap_config,
@@ -750,9 +885,21 @@ static const struct tegra_admaif_soc_data soc_data_tegra186 = {
750885
.rx_base = TEGRA186_ADMAIF_RX_BASE,
751886
};
752887

888+
static const struct tegra_admaif_soc_data soc_data_tegra264 = {
889+
.num_ch = TEGRA264_ADMAIF_CHANNEL_COUNT,
890+
.max_stream_ch = TEGRA264_ADMAIF_MAX_CHANNEL,
891+
.cmpnt = &tegra264_admaif_cmpnt,
892+
.dais = tegra264_admaif_cmpnt_dais,
893+
.regmap_conf = &tegra264_admaif_regmap_config,
894+
.global_base = TEGRA264_ADMAIF_GLOBAL_BASE,
895+
.tx_base = TEGRA264_ADMAIF_TX_BASE,
896+
.rx_base = TEGRA264_ADMAIF_RX_BASE,
897+
};
898+
753899
static const struct of_device_id tegra_admaif_of_match[] = {
754900
{ .compatible = "nvidia,tegra210-admaif", .data = &soc_data_tegra210 },
755901
{ .compatible = "nvidia,tegra186-admaif", .data = &soc_data_tegra186 },
902+
{ .compatible = "nvidia,tegra264-admaif", .data = &soc_data_tegra264 },
756903
{},
757904
};
758905
MODULE_DEVICE_TABLE(of, tegra_admaif_of_match);

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