1111
1212#include "amd_iommu_types.h"
1313
14- extern irqreturn_t amd_iommu_int_thread (int irq , void * data );
15- extern irqreturn_t amd_iommu_int_handler (int irq , void * data );
16- extern void amd_iommu_apply_erratum_63 (struct amd_iommu * iommu , u16 devid );
17- extern void amd_iommu_restart_event_logging (struct amd_iommu * iommu );
18- extern int amd_iommu_init_devices (void );
19- extern void amd_iommu_uninit_devices (void );
20- extern void amd_iommu_init_notifier (void );
21- extern void amd_iommu_set_rlookup_table (struct amd_iommu * iommu , u16 devid );
14+ irqreturn_t amd_iommu_int_thread (int irq , void * data );
15+ irqreturn_t amd_iommu_int_handler (int irq , void * data );
16+ void amd_iommu_apply_erratum_63 (struct amd_iommu * iommu , u16 devid );
17+ void amd_iommu_restart_event_logging (struct amd_iommu * iommu );
18+ int amd_iommu_init_devices (void );
19+ void amd_iommu_uninit_devices (void );
20+ void amd_iommu_init_notifier (void );
21+ void amd_iommu_set_rlookup_table (struct amd_iommu * iommu , u16 devid );
2222
2323#ifdef CONFIG_AMD_IOMMU_DEBUGFS
2424void amd_iommu_debugfs_setup (struct amd_iommu * iommu );
@@ -27,45 +27,44 @@ static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
2727#endif
2828
2929/* Needed for interrupt remapping */
30- extern int amd_iommu_prepare (void );
31- extern int amd_iommu_enable (void );
32- extern void amd_iommu_disable (void );
33- extern int amd_iommu_reenable (int );
34- extern int amd_iommu_enable_faulting (void );
30+ int amd_iommu_prepare (void );
31+ int amd_iommu_enable (void );
32+ void amd_iommu_disable (void );
33+ int amd_iommu_reenable (int mode );
34+ int amd_iommu_enable_faulting (void );
3535extern int amd_iommu_guest_ir ;
3636extern enum io_pgtable_fmt amd_iommu_pgtable ;
3737extern int amd_iommu_gpt_level ;
3838
3939/* IOMMUv2 specific functions */
4040struct iommu_domain ;
4141
42- extern bool amd_iommu_v2_supported (void );
43- extern struct amd_iommu * get_amd_iommu (unsigned int idx );
44- extern u8 amd_iommu_pc_get_max_banks (unsigned int idx );
45- extern bool amd_iommu_pc_supported (void );
46- extern u8 amd_iommu_pc_get_max_counters (unsigned int idx );
47- extern int amd_iommu_pc_get_reg (struct amd_iommu * iommu , u8 bank , u8 cntr ,
48- u8 fxn , u64 * value );
49- extern int amd_iommu_pc_set_reg (struct amd_iommu * iommu , u8 bank , u8 cntr ,
50- u8 fxn , u64 * value );
51-
52- extern int amd_iommu_register_ppr_notifier (struct notifier_block * nb );
53- extern int amd_iommu_unregister_ppr_notifier (struct notifier_block * nb );
54- extern void amd_iommu_domain_direct_map (struct iommu_domain * dom );
55- extern int amd_iommu_domain_enable_v2 (struct iommu_domain * dom , int pasids );
56- extern int amd_iommu_flush_page (struct iommu_domain * dom , u32 pasid ,
57- u64 address );
58- extern void amd_iommu_update_and_flush_device_table (struct protection_domain * domain );
59- extern void amd_iommu_domain_update (struct protection_domain * domain );
60- extern void amd_iommu_domain_flush_complete (struct protection_domain * domain );
61- extern void amd_iommu_domain_flush_tlb_pde (struct protection_domain * domain );
62- extern int amd_iommu_flush_tlb (struct iommu_domain * dom , u32 pasid );
63- extern int amd_iommu_domain_set_gcr3 (struct iommu_domain * dom , u32 pasid ,
64- unsigned long cr3 );
65- extern int amd_iommu_domain_clear_gcr3 (struct iommu_domain * dom , u32 pasid );
42+ bool amd_iommu_v2_supported (void );
43+ struct amd_iommu * get_amd_iommu (unsigned int idx );
44+ u8 amd_iommu_pc_get_max_banks (unsigned int idx );
45+ bool amd_iommu_pc_supported (void );
46+ u8 amd_iommu_pc_get_max_counters (unsigned int idx );
47+ int amd_iommu_pc_get_reg (struct amd_iommu * iommu , u8 bank , u8 cntr ,
48+ u8 fxn , u64 * value );
49+ int amd_iommu_pc_set_reg (struct amd_iommu * iommu , u8 bank , u8 cntr ,
50+ u8 fxn , u64 * value );
51+
52+ int amd_iommu_register_ppr_notifier (struct notifier_block * nb );
53+ int amd_iommu_unregister_ppr_notifier (struct notifier_block * nb );
54+ void amd_iommu_domain_direct_map (struct iommu_domain * dom );
55+ int amd_iommu_domain_enable_v2 (struct iommu_domain * dom , int pasids );
56+ int amd_iommu_flush_page (struct iommu_domain * dom , u32 pasid , u64 address );
57+ void amd_iommu_update_and_flush_device_table (struct protection_domain * domain );
58+ void amd_iommu_domain_update (struct protection_domain * domain );
59+ void amd_iommu_domain_flush_complete (struct protection_domain * domain );
60+ void amd_iommu_domain_flush_tlb_pde (struct protection_domain * domain );
61+ int amd_iommu_flush_tlb (struct iommu_domain * dom , u32 pasid );
62+ int amd_iommu_domain_set_gcr3 (struct iommu_domain * dom , u32 pasid ,
63+ unsigned long cr3 );
64+ int amd_iommu_domain_clear_gcr3 (struct iommu_domain * dom , u32 pasid );
6665
6766#ifdef CONFIG_IRQ_REMAP
68- extern int amd_iommu_create_irq_domain (struct amd_iommu * iommu );
67+ int amd_iommu_create_irq_domain (struct amd_iommu * iommu );
6968#else
7069static inline int amd_iommu_create_irq_domain (struct amd_iommu * iommu )
7170{
@@ -77,8 +76,8 @@ static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
7776#define PPR_INVALID 0x1
7877#define PPR_FAILURE 0xf
7978
80- extern int amd_iommu_complete_ppr (struct pci_dev * pdev , u32 pasid ,
81- int status , int tag );
79+ int amd_iommu_complete_ppr (struct pci_dev * pdev , u32 pasid ,
80+ int status , int tag );
8281
8382static inline bool is_rd890_iommu (struct pci_dev * pdev )
8483{
@@ -131,20 +130,19 @@ static inline void *alloc_pgtable_page(int nid, gfp_t gfp)
131130 return page ? page_address (page ) : NULL ;
132131}
133132
134- extern bool translation_pre_enabled (struct amd_iommu * iommu );
135- extern bool amd_iommu_is_attach_deferred (struct device * dev );
136- extern int __init add_special_device (u8 type , u8 id , u32 * devid ,
137- bool cmd_line );
133+ bool translation_pre_enabled (struct amd_iommu * iommu );
134+ bool amd_iommu_is_attach_deferred (struct device * dev );
135+ int __init add_special_device (u8 type , u8 id , u32 * devid , bool cmd_line );
138136
139137#ifdef CONFIG_DMI
140138void amd_iommu_apply_ivrs_quirks (void );
141139#else
142140static inline void amd_iommu_apply_ivrs_quirks (void ) { }
143141#endif
144142
145- extern void amd_iommu_domain_set_pgtable (struct protection_domain * domain ,
146- u64 * root , int mode );
147- extern struct dev_table_entry * get_dev_table (struct amd_iommu * iommu );
143+ void amd_iommu_domain_set_pgtable (struct protection_domain * domain ,
144+ u64 * root , int mode );
145+ struct dev_table_entry * get_dev_table (struct amd_iommu * iommu );
148146
149147extern u64 amd_iommu_efr ;
150148extern u64 amd_iommu_efr2 ;
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