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28 | 28 | #define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1) |
29 | 29 | #define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1) |
30 | 30 | #define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1) |
31 | | -#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) |
| 31 | +#define CLKS_NR_PERI (CLK_GOUT_BUSIF_TMU_PCLK + 1) |
32 | 32 | #define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1) |
33 | 33 | #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1) |
34 | 34 |
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@@ -1921,6 +1921,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { |
1921 | 1921 | #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c |
1922 | 1922 | #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 |
1923 | 1923 | #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 |
| 1924 | +#define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK 0x2018 |
1924 | 1925 | #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 |
1925 | 1926 | #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 |
1926 | 1927 | #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 |
@@ -1957,6 +1958,7 @@ static const unsigned long peri_clk_regs[] __initconst = { |
1957 | 1958 | CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, |
1958 | 1959 | CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, |
1959 | 1960 | CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, |
| 1961 | + CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, |
1960 | 1962 | CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, |
1961 | 1963 | CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, |
1962 | 1964 | CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, |
@@ -2068,6 +2070,9 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = { |
2068 | 2070 | GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", |
2069 | 2071 | "mout_peri_bus_user", |
2070 | 2072 | CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), |
| 2073 | + GATE(CLK_GOUT_BUSIF_TMU_PCLK, "gout_busif_tmu_pclk", |
| 2074 | + "mout_peri_bus_user", |
| 2075 | + CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, 21, 0, 0), |
2071 | 2076 | }; |
2072 | 2077 |
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2073 | 2078 | static const struct samsung_cmu_info peri_cmu_info __initconst = { |
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