Skip to content

Commit 7cbe799

Browse files
Kaustabh Chakrabortystorulf
Kaustabh Chakraborty
authored and
storulf
committed
mmc: dw_mmc: add exynos7870 DW MMC support
Add support for Exynos7870 DW MMC controllers, for both SMU and non-SMU variants. These controllers require a quirk to access 64-bit FIFO in 32-bit accesses (DW_MMC_QUIRK_FIFO64_32). Signed-off-by: Kaustabh Chakraborty <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
1 parent 57c0902 commit 7cbe799

File tree

1 file changed

+40
-1
lines changed

1 file changed

+40
-1
lines changed

‎drivers/mmc/host/dw_mmc-exynos.c‎

Lines changed: 40 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,8 @@ enum dw_mci_exynos_type {
2727
DW_MCI_TYPE_EXYNOS5420_SMU,
2828
DW_MCI_TYPE_EXYNOS7,
2929
DW_MCI_TYPE_EXYNOS7_SMU,
30+
DW_MCI_TYPE_EXYNOS7870,
31+
DW_MCI_TYPE_EXYNOS7870_SMU,
3032
DW_MCI_TYPE_ARTPEC8,
3133
};
3234

@@ -69,6 +71,12 @@ static struct dw_mci_exynos_compatible {
6971
}, {
7072
.compatible = "samsung,exynos7-dw-mshc-smu",
7173
.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
74+
}, {
75+
.compatible = "samsung,exynos7870-dw-mshc",
76+
.ctrl_type = DW_MCI_TYPE_EXYNOS7870,
77+
}, {
78+
.compatible = "samsung,exynos7870-dw-mshc-smu",
79+
.ctrl_type = DW_MCI_TYPE_EXYNOS7870_SMU,
7280
}, {
7381
.compatible = "axis,artpec8-dw-mshc",
7482
.ctrl_type = DW_MCI_TYPE_ARTPEC8,
@@ -85,6 +93,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
8593
return EXYNOS4210_FIXED_CIU_CLK_DIV;
8694
else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
8795
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
96+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
97+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
8898
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
8999
return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
90100
else
@@ -100,7 +110,8 @@ static void dw_mci_exynos_config_smu(struct dw_mci *host)
100110
* set for non-ecryption mode at this time.
101111
*/
102112
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
103-
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
113+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
114+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU) {
104115
mci_writel(host, MPSBEGIN0, 0);
105116
mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
106117
mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
@@ -126,6 +137,12 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
126137
DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
127138
}
128139

140+
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
141+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU) {
142+
/* Quirk needed for certain Exynos SoCs */
143+
host->quirks |= DW_MMC_QUIRK_FIFO64_32;
144+
}
145+
129146
if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) {
130147
/* Quirk needed for the ARTPEC-8 SoC */
131148
host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT;
@@ -143,6 +160,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
143160

144161
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
145162
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
163+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
164+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
146165
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
147166
clksel = mci_readl(host, CLKSEL64);
148167
else
@@ -152,6 +171,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
152171

153172
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
154173
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
174+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
175+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
155176
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
156177
mci_writel(host, CLKSEL64, clksel);
157178
else
@@ -222,6 +243,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev)
222243

223244
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
224245
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
246+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
247+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
225248
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
226249
clksel = mci_readl(host, CLKSEL64);
227250
else
@@ -230,6 +253,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev)
230253
if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
231254
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
232255
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
256+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
257+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
233258
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
234259
mci_writel(host, CLKSEL64, clksel);
235260
else
@@ -409,6 +434,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
409434

410435
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
411436
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
437+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
438+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
412439
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
413440
return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
414441
else
@@ -422,13 +449,17 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
422449

423450
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
424451
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
452+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
453+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
425454
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
426455
clksel = mci_readl(host, CLKSEL64);
427456
else
428457
clksel = mci_readl(host, CLKSEL);
429458
clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
430459
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
431460
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
461+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
462+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
432463
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
433464
mci_writel(host, CLKSEL64, clksel);
434465
else
@@ -443,6 +474,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
443474

444475
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
445476
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
477+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
478+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
446479
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
447480
clksel = mci_readl(host, CLKSEL64);
448481
else
@@ -453,6 +486,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
453486

454487
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
455488
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
489+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
490+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
456491
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
457492
mci_writel(host, CLKSEL64, clksel);
458493
else
@@ -632,6 +667,10 @@ static const struct of_device_id dw_mci_exynos_match[] = {
632667
.data = &exynos_drv_data, },
633668
{ .compatible = "samsung,exynos7-dw-mshc-smu",
634669
.data = &exynos_drv_data, },
670+
{ .compatible = "samsung,exynos7870-dw-mshc",
671+
.data = &exynos_drv_data, },
672+
{ .compatible = "samsung,exynos7870-dw-mshc-smu",
673+
.data = &exynos_drv_data, },
635674
{ .compatible = "axis,artpec8-dw-mshc",
636675
.data = &artpec_drv_data, },
637676
{},

0 commit comments

Comments
 (0)