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Merge tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull generic phy updates from Vinod Koul: "New HW Support: - Support for Embedded DisplayPort and DisplayPort submodes and driver support on Qualcomm X1E80100 edp driver - Qualcomm QMP UFS PHY for SM8475, QMP USB phy for QDU1000/QRU1000 and eusb2-repeater for SMB2360 - Samsung HDMI PHY for i.MX8MP, gs101 UFS phy - Mediatek XFI T-PHY support for mt7988 - Rockchip usbdp combo phy driver Updates: - Qualcomm x4 lane EP support for sa8775p, v4 ad v6 support for X1E80100, SM8650 tables for UFS Gear 4 & 5 and correct voltage swing tables - Freescale imx8m-pci pcie link-up updates - Rockchip rx-common-refclk-mode support - More platform remove callback returning void conversions" * tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000 dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000 phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p phy: samsung-ufs: ufs: exit on first reported error phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h header phy: rockchip: fix CONFIG_TYPEC dependency phy: rockchip: usbdp: fix uninitialized variable phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode phy: rockchip: add usbdp combo phy driver dt-bindings: phy: add rockchip usbdp combo phy document phy: add driver for MediaTek XFI T-PHY dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindings phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5 MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101. ...
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‎Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8MP HDMI PHY
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maintainers:
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- Lucas Stach <[email protected]>
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properties:
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compatible:
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enum:
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- fsl,imx8mp-hdmi-phy
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reg:
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maxItems: 1
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"#clock-cells":
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const: 0
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: apb
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- const: ref
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"#phy-cells":
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const: 0
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- "#clock-cells"
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- clocks
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- clock-names
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- "#phy-cells"
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/power/imx8mp-power.h>
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phy@32fdff00 {
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compatible = "fsl,imx8mp-hdmi-phy";
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reg = <0x32fdff00 0x100>;
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clocks = <&clk IMX8MP_CLK_HDMI_APB>,
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<&clk IMX8MP_CLK_HDMI_24M>;
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clock-names = "apb", "ref";
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power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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};

‎Documentation/devicetree/bindings/phy/mediatek,mt7988-xfi-tphy.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT7988 XFI T-PHY
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maintainers:
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- Daniel Golle <[email protected]>
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description:
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The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
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used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
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MediaTek's 10G-capabale MT7988 SoC.
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In MediaTek's SDK sources, this unit is referred to as "pextp".
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properties:
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compatible:
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const: mediatek,mt7988-xfi-tphy
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reg:
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maxItems: 1
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clocks:
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items:
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- description: XFI PHY clock
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- description: XFI register clock
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clock-names:
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items:
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- const: xfipll
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- const: topxtal
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resets:
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items:
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- description: Reset controller corresponding to the phy instance.
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mediatek,usxgmii-performance-errata:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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One instance of the T-PHY on MT7988 suffers from a performance
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problem in 10GBase-R mode which needs a work-around in the driver.
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This flag enables a work-around ajusting an analog phy setting and
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is required for XFI Port0 of the MT7988 SoC to be in compliance with
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the SFP specification.
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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phy@11f20000 {
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compatible = "mediatek,mt7988-xfi-tphy";
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reg = <0 0x11f20000 0 0x10000>;
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clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
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<&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
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clock-names = "xfipll", "topxtal";
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resets = <&watchdog 14>;
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mediatek,usxgmii-performance-errata;
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#phy-cells = <0>;
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};
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};
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...

‎Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip USBDP Combo PHY with Samsung IP block
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maintainers:
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- Frank Wang <[email protected]>
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- Zhang Yubing <[email protected]>
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properties:
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compatible:
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enum:
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- rockchip,rk3588-usbdp-phy
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reg:
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maxItems: 1
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"#phy-cells":
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description: |
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Cell allows setting the type of the PHY. Possible values are:
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- PHY_TYPE_USB3
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- PHY_TYPE_DP
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const: 1
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: refclk
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- const: immortal
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- const: pclk
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- const: utmi
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resets:
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maxItems: 5
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reset-names:
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items:
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- const: init
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- const: cmn
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- const: lane
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- const: pcs_apb
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- const: pma_apb
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rockchip,dp-lane-mux:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 2
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maxItems: 4
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items:
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maximum: 3
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description:
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An array of physical Type-C lanes indexes. Position of an entry
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determines the DisplayPort (DP) lane index, while the value of an entry
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indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
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e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
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3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
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lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
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<0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
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phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
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DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
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rockchip,u2phy-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'usb2 phy general register files'.
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rockchip,usb-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'usb general register files'.
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rockchip,usbdpphy-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'usbdp phy general register files'.
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rockchip,vo-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'video output general register files'.
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When select the DP lane mapping will request its phandle.
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sbu1-dc-gpios:
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description:
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GPIO connected to the SBU1 line of the USB-C connector via a big resistor
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(~100K) to apply a DC offset for signalling the connector orientation.
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maxItems: 1
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sbu2-dc-gpios:
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description:
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GPIO connected to the SBU2 line of the USB-C connector via a big resistor
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(~100K) to apply a DC offset for signalling the connector orientation.
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maxItems: 1
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orientation-switch:
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description: Flag the port as possible handler of orientation switching
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type: boolean
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mode-switch:
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description: Flag the port as possible handler of altmode switching
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type: boolean
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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A port node to link the PHY to a TypeC controller for the purpose of
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handling orientation switching.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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usbdp_phy0: phy@fed80000 {
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compatible = "rockchip,rk3588-usbdp-phy";
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reg = <0xfed80000 0x10000>;
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#phy-cells = <1>;
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clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
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<&cru CLK_USBDP_PHY0_IMMORTAL>,
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<&cru PCLK_USBDPPHY0>,
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<&u2phy0>;
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clock-names = "refclk", "immortal", "pclk", "utmi";
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resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
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<&cru SRST_USBDP_COMBO_PHY0_CMN>,
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<&cru SRST_USBDP_COMBO_PHY0_LANE>,
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<&cru SRST_USBDP_COMBO_PHY0_PCS>,
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<&cru SRST_P_USBDPPHY0>;
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reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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rockchip,u2phy-grf = <&usb2phy0_grf>;
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rockchip,usb-grf = <&usb_grf>;
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rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
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rockchip,vo-grf = <&vo0_grf>;
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};

‎Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml‎

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- qcom,sc8180x-edp-phy
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- qcom,sc8280xp-dp-phy
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- qcom,sc8280xp-edp-phy
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- qcom,x1e80100-dp-phy
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reg:
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items:

‎Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml‎

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- description: offset of PCIe 4-lane configuration register
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- description: offset of configuration bit for this PHY
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"#clock-cells":
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const: 0
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"#clock-cells": true
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clock-output-names:
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maxItems: 1
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minItems: 1
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maxItems: 2
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"#phy-cells":
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const: 0
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enum:
199199
- qcom,sm8550-qmp-gen4x2-pcie-phy
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- qcom,sm8650-qmp-gen4x2-pcie-phy
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- qcom,x1e80100-qmp-gen3x2-pcie-phy
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- qcom,x1e80100-qmp-gen4x2-pcie-phy
203202
then:
204203
properties:
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213212
reset-names:
214213
maxItems: 1
215214

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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-qmp-gen4x2-pcie-phy
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- qcom,sm8550-qmp-gen4x2-pcie-phy
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- qcom,sm8650-qmp-gen4x2-pcie-phy
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then:
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properties:
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clock-output-names:
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minItems: 2
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"#clock-cells":
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const: 1
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else:
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properties:
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clock-output-names:
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maxItems: 1
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"#clock-cells":
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const: 0
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

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