@@ -1648,16 +1648,17 @@ static int nvmet_pci_epf_process_sq(struct nvmet_pci_epf_ctrl *ctrl,
16481648{
16491649 struct nvmet_pci_epf_iod * iod ;
16501650 int ret , n = 0 ;
1651+ u16 head = sq -> head ;
16511652
16521653 sq -> tail = nvmet_pci_epf_bar_read32 (ctrl , sq -> db );
1653- while (sq -> head != sq -> tail && (!ctrl -> sq_ab || n < ctrl -> sq_ab )) {
1654+ while (head != sq -> tail && (!ctrl -> sq_ab || n < ctrl -> sq_ab )) {
16541655 iod = nvmet_pci_epf_alloc_iod (sq );
16551656 if (!iod )
16561657 break ;
16571658
16581659 /* Get the NVMe command submitted by the host. */
16591660 ret = nvmet_pci_epf_transfer (ctrl , & iod -> cmd ,
1660- sq -> pci_addr + sq -> head * sq -> qes ,
1661+ sq -> pci_addr + head * sq -> qes ,
16611662 sq -> qes , DMA_FROM_DEVICE );
16621663 if (ret ) {
16631664 /* Not much we can do... */
@@ -1666,12 +1667,13 @@ static int nvmet_pci_epf_process_sq(struct nvmet_pci_epf_ctrl *ctrl,
16661667 }
16671668
16681669 dev_dbg (ctrl -> dev , "SQ[%u]: head %u, tail %u, command %s\n" ,
1669- sq -> qid , sq -> head , sq -> tail ,
1670+ sq -> qid , head , sq -> tail ,
16701671 nvmet_pci_epf_iod_name (iod ));
16711672
1672- sq -> head ++ ;
1673- if (sq -> head == sq -> depth )
1674- sq -> head = 0 ;
1673+ head ++ ;
1674+ if (head == sq -> depth )
1675+ head = 0 ;
1676+ WRITE_ONCE (sq -> head , head );
16751677 n ++ ;
16761678
16771679 queue_work_on (WORK_CPU_UNBOUND , sq -> iod_wq , & iod -> work );
@@ -1761,8 +1763,17 @@ static void nvmet_pci_epf_cq_work(struct work_struct *work)
17611763 if (!iod )
17621764 break ;
17631765
1764- /* Post the IOD completion entry. */
1766+ /*
1767+ * Post the IOD completion entry. If the IOD request was
1768+ * executed (req->execute() called), the CQE is already
1769+ * initialized. However, the IOD may have been failed before
1770+ * that, leaving the CQE not properly initialized. So always
1771+ * initialize it here.
1772+ */
17651773 cqe = & iod -> cqe ;
1774+ cqe -> sq_head = cpu_to_le16 (READ_ONCE (iod -> sq -> head ));
1775+ cqe -> sq_id = cpu_to_le16 (iod -> sq -> qid );
1776+ cqe -> command_id = iod -> cmd .common .command_id ;
17661777 cqe -> status = cpu_to_le16 ((iod -> status << 1 ) | cq -> phase );
17671778
17681779 dev_dbg (ctrl -> dev ,
@@ -1800,6 +1811,21 @@ static void nvmet_pci_epf_cq_work(struct work_struct *work)
18001811 NVMET_PCI_EPF_CQ_RETRY_INTERVAL );
18011812}
18021813
1814+ static void nvmet_pci_epf_clear_ctrl_config (struct nvmet_pci_epf_ctrl * ctrl )
1815+ {
1816+ struct nvmet_ctrl * tctrl = ctrl -> tctrl ;
1817+
1818+ /* Initialize controller status. */
1819+ tctrl -> csts = 0 ;
1820+ ctrl -> csts = 0 ;
1821+ nvmet_pci_epf_bar_write32 (ctrl , NVME_REG_CSTS , ctrl -> csts );
1822+
1823+ /* Initialize controller configuration and start polling. */
1824+ tctrl -> cc = 0 ;
1825+ ctrl -> cc = 0 ;
1826+ nvmet_pci_epf_bar_write32 (ctrl , NVME_REG_CC , ctrl -> cc );
1827+ }
1828+
18031829static int nvmet_pci_epf_enable_ctrl (struct nvmet_pci_epf_ctrl * ctrl )
18041830{
18051831 u64 pci_addr , asq , acq ;
@@ -1865,18 +1891,20 @@ static int nvmet_pci_epf_enable_ctrl(struct nvmet_pci_epf_ctrl *ctrl)
18651891 return 0 ;
18661892
18671893err :
1868- ctrl -> csts = 0 ;
1894+ nvmet_pci_epf_clear_ctrl_config ( ctrl ) ;
18691895 return - EINVAL ;
18701896}
18711897
1872- static void nvmet_pci_epf_disable_ctrl (struct nvmet_pci_epf_ctrl * ctrl )
1898+ static void nvmet_pci_epf_disable_ctrl (struct nvmet_pci_epf_ctrl * ctrl ,
1899+ bool shutdown )
18731900{
18741901 int qid ;
18751902
18761903 if (!ctrl -> enabled )
18771904 return ;
18781905
1879- dev_info (ctrl -> dev , "Disabling controller\n" );
1906+ dev_info (ctrl -> dev , "%s controller\n" ,
1907+ shutdown ? "Shutting down" : "Disabling" );
18801908
18811909 ctrl -> enabled = false;
18821910 cancel_delayed_work_sync (& ctrl -> poll_sqs );
@@ -1893,6 +1921,11 @@ static void nvmet_pci_epf_disable_ctrl(struct nvmet_pci_epf_ctrl *ctrl)
18931921 nvmet_pci_epf_delete_cq (ctrl -> tctrl , 0 );
18941922
18951923 ctrl -> csts &= ~NVME_CSTS_RDY ;
1924+ if (shutdown ) {
1925+ ctrl -> csts |= NVME_CSTS_SHST_CMPLT ;
1926+ ctrl -> cc &= ~NVME_CC_ENABLE ;
1927+ nvmet_pci_epf_bar_write32 (ctrl , NVME_REG_CC , ctrl -> cc );
1928+ }
18961929}
18971930
18981931static void nvmet_pci_epf_poll_cc_work (struct work_struct * work )
@@ -1919,12 +1952,10 @@ static void nvmet_pci_epf_poll_cc_work(struct work_struct *work)
19191952 }
19201953
19211954 if (!nvmet_cc_en (new_cc ) && nvmet_cc_en (old_cc ))
1922- nvmet_pci_epf_disable_ctrl (ctrl );
1955+ nvmet_pci_epf_disable_ctrl (ctrl , false );
19231956
1924- if (nvmet_cc_shn (new_cc ) && !nvmet_cc_shn (old_cc )) {
1925- nvmet_pci_epf_disable_ctrl (ctrl );
1926- ctrl -> csts |= NVME_CSTS_SHST_CMPLT ;
1927- }
1957+ if (nvmet_cc_shn (new_cc ) && !nvmet_cc_shn (old_cc ))
1958+ nvmet_pci_epf_disable_ctrl (ctrl , true);
19281959
19291960 if (!nvmet_cc_shn (new_cc ) && nvmet_cc_shn (old_cc ))
19301961 ctrl -> csts &= ~NVME_CSTS_SHST_CMPLT ;
@@ -1963,16 +1994,10 @@ static void nvmet_pci_epf_init_bar(struct nvmet_pci_epf_ctrl *ctrl)
19631994 /* Clear Controller Memory Buffer Supported (CMBS). */
19641995 ctrl -> cap &= ~(0x1ULL << 57 );
19651996
1966- /* Controller configuration. */
1967- ctrl -> cc = tctrl -> cc & (~NVME_CC_ENABLE );
1968-
1969- /* Controller status. */
1970- ctrl -> csts = ctrl -> tctrl -> csts ;
1971-
19721997 nvmet_pci_epf_bar_write64 (ctrl , NVME_REG_CAP , ctrl -> cap );
19731998 nvmet_pci_epf_bar_write32 (ctrl , NVME_REG_VS , tctrl -> subsys -> ver );
1974- nvmet_pci_epf_bar_write32 ( ctrl , NVME_REG_CSTS , ctrl -> csts );
1975- nvmet_pci_epf_bar_write32 (ctrl , NVME_REG_CC , ctrl -> cc );
1999+
2000+ nvmet_pci_epf_clear_ctrl_config (ctrl );
19762001}
19772002
19782003static int nvmet_pci_epf_create_ctrl (struct nvmet_pci_epf * nvme_epf ,
@@ -2070,14 +2095,22 @@ static int nvmet_pci_epf_create_ctrl(struct nvmet_pci_epf *nvme_epf,
20702095
20712096static void nvmet_pci_epf_start_ctrl (struct nvmet_pci_epf_ctrl * ctrl )
20722097{
2098+
2099+ dev_info (ctrl -> dev , "PCI link up\n" );
2100+ ctrl -> link_up = true;
2101+
20732102 schedule_delayed_work (& ctrl -> poll_cc , NVMET_PCI_EPF_CC_POLL_INTERVAL );
20742103}
20752104
20762105static void nvmet_pci_epf_stop_ctrl (struct nvmet_pci_epf_ctrl * ctrl )
20772106{
2107+ dev_info (ctrl -> dev , "PCI link down\n" );
2108+ ctrl -> link_up = false;
2109+
20782110 cancel_delayed_work_sync (& ctrl -> poll_cc );
20792111
2080- nvmet_pci_epf_disable_ctrl (ctrl );
2112+ nvmet_pci_epf_disable_ctrl (ctrl , false);
2113+ nvmet_pci_epf_clear_ctrl_config (ctrl );
20812114}
20822115
20832116static void nvmet_pci_epf_destroy_ctrl (struct nvmet_pci_epf_ctrl * ctrl )
@@ -2300,10 +2333,8 @@ static int nvmet_pci_epf_epc_init(struct pci_epf *epf)
23002333 if (ret )
23012334 goto out_clear_bar ;
23022335
2303- if (!epc_features -> linkup_notifier ) {
2304- ctrl -> link_up = true;
2336+ if (!epc_features -> linkup_notifier )
23052337 nvmet_pci_epf_start_ctrl (& nvme_epf -> ctrl );
2306- }
23072338
23082339 return 0 ;
23092340
@@ -2319,7 +2350,6 @@ static void nvmet_pci_epf_epc_deinit(struct pci_epf *epf)
23192350 struct nvmet_pci_epf * nvme_epf = epf_get_drvdata (epf );
23202351 struct nvmet_pci_epf_ctrl * ctrl = & nvme_epf -> ctrl ;
23212352
2322- ctrl -> link_up = false;
23232353 nvmet_pci_epf_destroy_ctrl (ctrl );
23242354
23252355 nvmet_pci_epf_deinit_dma (nvme_epf );
@@ -2331,7 +2361,6 @@ static int nvmet_pci_epf_link_up(struct pci_epf *epf)
23312361 struct nvmet_pci_epf * nvme_epf = epf_get_drvdata (epf );
23322362 struct nvmet_pci_epf_ctrl * ctrl = & nvme_epf -> ctrl ;
23332363
2334- ctrl -> link_up = true;
23352364 nvmet_pci_epf_start_ctrl (ctrl );
23362365
23372366 return 0 ;
@@ -2342,7 +2371,6 @@ static int nvmet_pci_epf_link_down(struct pci_epf *epf)
23422371 struct nvmet_pci_epf * nvme_epf = epf_get_drvdata (epf );
23432372 struct nvmet_pci_epf_ctrl * ctrl = & nvme_epf -> ctrl ;
23442373
2345- ctrl -> link_up = false;
23462374 nvmet_pci_epf_stop_ctrl (ctrl );
23472375
23482376 return 0 ;
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