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Merge tag 'qcom-clk-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson: - Add camera, display and GPU clock drivers for Qualcomm SM4450 - Add a camera clock driver for Qualcomm SM8150 - Mark a bunch of struct freq_tbl const to reduce .data usage - Add Qualcomm MSM8226 A7PLL and Regera PLL support - Fix the Qualcomm Lucid 5LPE PLL configuration sequence to not reuse Trion, as they do differ - A number of fixes to the Qualcomm SM8550 display clock driver - Fold Qualcomm SM8650 display clock driver into SM8550 one - Add missing clocks and GDSCs needed for audio on Qualcomm MSM8998 - Add missing USB MP resets, GPLL9, and QUPv3 DFS to Qualcomm SC8180X - Fix sdcc clk frequency tables on Qualcomm SC8180X - Drop the Qualcomm SM8150 gcc_cpuss_ahb_clk_src - Mark Qualcomm PCIe GDSCs as RET_ON on sm8250 and sm8540 to avoid them turning off during suspend - Use the HW_CTRL mechanism on Qualcomm SM8550 video clock controller GDSCs * tag 'qcom-clk-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (47 commits) clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details dt-bindings: interconnect: Add Qualcomm IPQ5332 support clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions clk: qcom: Fix SM_CAMCC_8150 dependencies clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table clk: qcom: gcc-sc8180x: Add GPLL9 support dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x clk: qcom: clk-rpmh: Fix overflow in BCM vote dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema dt-bindings: clock: Add x1e80100 LPASSCC reset controller ...
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lines changed

‎Documentation/devicetree/bindings/clock/qcom,a53pll.yaml‎

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- qcom,ipq6018-a53pll
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- qcom,ipq8074-a53pll
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- qcom,ipq9574-a73pll
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- qcom,msm8226-a7pll
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- qcom,msm8916-a53pll
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- qcom,msm8939-a53pll
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@@ -40,6 +41,9 @@ properties:
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml‎

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- description: USB PCIE wrapper pipe clock source
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'#power-domain-cells': false
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'#interconnect-cells':
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const: 1
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required:
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- compatible

‎Documentation/devicetree/bindings/clock/qcom,qcs404-turingcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Turing Clock & Reset Controller on QCS404
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maintainers:
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- Bjorn Andersson <[email protected]>
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properties:
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compatible:
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const: qcom,qcs404-turingcc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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clock-controller@800000 {
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compatible = "qcom,qcs404-turingcc";
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reg = <0x00800000 0x30000>;
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clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml‎

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properties:
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compatible:
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enum:
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- qcom,sc8280xp-lpassaudiocc
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- qcom,sc8280xp-lpasscc
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oneOf:
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- enum:
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- qcom,sc8280xp-lpassaudiocc
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- qcom,sc8280xp-lpasscc
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- items:
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- const: qcom,x1e80100-lpassaudiocc
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- const: qcom,sc8280xp-lpassaudiocc
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- items:
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- const: qcom,x1e80100-lpasscc
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- const: qcom,sc8280xp-lpasscc
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reg:
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maxItems: 1

‎Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Camera Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <[email protected]>
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- Taniya Das <[email protected]>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and power
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domains on SM4450
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See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
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properties:
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compatible:
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const: qcom,sm4450-camcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Camera AHB clock source from GCC
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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clock-controller@ade0000 {
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compatible = "qcom,sm4450-camcc";
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reg = <0x0ade0000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_CAMERA_AHB_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <[email protected]>
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- Taniya Das <[email protected]>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM4450
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See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
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properties:
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compatible:
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const: qcom,sm4450-dispcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Display AHB clock source from GCC
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- description: sleep clock source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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clock-controller@af00000 {
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compatible = "qcom,sm4450-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&dsi0_phy_pll_out_byteclk>,
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<&dsi0_phy_pll_out_dsiclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm8150-camcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Camera Clock & Reset Controller on SM8150
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maintainers:
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- Satya Priya Kakitapalli <[email protected]>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and
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power domains on SM8150.
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See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
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properties:
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compatible:
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const: qcom,sm8150-camcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Camera AHB clock from GCC
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power-domains:
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maxItems: 1
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description:
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A phandle and PM domain specifier for the MMCX power domain.
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required-opps:
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maxItems: 1
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description:
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A phandle to an OPP node describing required MMCX performance point.
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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- required-opps
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
64+
#include <dt-bindings/clock/qcom,rpmh.h>
65+
#include <dt-bindings/power/qcom-rpmpd.h>
66+
clock-controller@ad00000 {
67+
compatible = "qcom,sm8150-camcc";
68+
reg = <0x0ad00000 0x10000>;
69+
clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_CAMERA_AHB_CLK>;
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power-domains = <&rpmhpd SM8150_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml‎

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include/dt-bindings/clock/qcom,sm8650-camcc.h
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include/dt-bindings/clock/qcom,x1e80100-camcc.h
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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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enum:
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- compatible
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- clocks
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- power-domains
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- required-opps
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allOf:
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- $ref: qcom,gcc.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc8280xp-camcc
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- qcom,sm8450-camcc
67+
- qcom,sm8550-camcc
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- qcom,x1e80100-camcc
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then:
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required:
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- required-opps
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unevaluatedProperties: false
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‎Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml‎

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domains on Qualcomm SoCs.
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See also::
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include/dt-bindings/clock/qcom,sm4450-gpucc.h
1718
include/dt-bindings/clock/qcom,sm8450-gpucc.h
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include/dt-bindings/clock/qcom,sm8550-gpucc.h
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include/dt-bindings/reset/qcom,sm8450-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,sm4450-gpucc
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- qcom,sm8450-gpucc
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- qcom,sm8550-gpucc
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- qcom,sm8650-gpucc

‎Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml‎

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- compatible
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- clocks
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- power-domains
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- required-opps
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-videocc
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- qcom,sm8550-videocc
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then:
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required:
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- required-opps
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unevaluatedProperties: false
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