@@ -23,106 +23,32 @@ struct ufs_renesas_priv {
2323 bool initialized ; /* The hardware needs initialization once */
2424};
2525
26- enum ufs_renesas_init_param_mode {
27- MODE_POLL ,
28- MODE_READ ,
29- MODE_WAIT ,
30- MODE_WRITE ,
31- };
32-
33- struct ufs_renesas_init_param {
34- enum ufs_renesas_init_param_mode mode ;
35- u32 reg ;
36- union {
37- u32 expected ;
38- u32 delay_us ;
39- u32 val ;
40- } u ;
41- u32 mask ;
42- u32 index ;
43- };
44-
4526static void ufs_renesas_dbg_register_dump (struct ufs_hba * hba )
4627{
4728 ufshcd_dump_regs (hba , 0xc0 , 0x40 , "regs: 0xc0 + " );
4829}
4930
50- static u32 ufs_renesas_reg_control (struct ufs_hba * hba ,
51- const struct ufs_renesas_init_param * p )
52- {
53- u32 val = 0 ;
54- int ret ;
55-
56- switch (p -> mode ) {
57- case MODE_POLL :
58- ret = readl_poll_timeout_atomic (hba -> mmio_base + p -> reg ,
59- val ,
60- (val & p -> mask ) == p -> u .expected ,
61- 10 , 1000 );
62- if (ret )
63- dev_err (hba -> dev , "%s: poll failed %d (%08x, %08x, %08x)\n" ,
64- __func__ , ret , val , p -> mask , p -> u .expected );
65- break ;
66- case MODE_READ :
67- val = ufshcd_readl (hba , p -> reg );
68- break ;
69- case MODE_WAIT :
70- if (p -> u .delay_us > 1000 )
71- mdelay (DIV_ROUND_UP (p -> u .delay_us , 1000 ));
72- else
73- udelay (p -> u .delay_us );
74- break ;
75- case MODE_WRITE :
76- ufshcd_writel (hba , p -> u .val , p -> reg );
77- break ;
78- default :
79- break ;
80- }
81-
82- return val ;
83- }
84-
8531static void ufs_renesas_poll (struct ufs_hba * hba , u32 reg , u32 expected , u32 mask )
8632{
87- struct ufs_renesas_init_param param = {
88- .mode = MODE_POLL ,
89- .reg = reg ,
90- .u .expected = expected ,
91- .mask = mask ,
92- };
93-
94- ufs_renesas_reg_control (hba , & param );
33+ int ret ;
34+ u32 val ;
35+
36+ ret = readl_poll_timeout_atomic (hba -> mmio_base + reg ,
37+ val , (val & mask ) == expected ,
38+ 10 , 1000 );
39+ if (ret )
40+ dev_err (hba -> dev , "%s: poll failed %d (%08x, %08x, %08x)\n" ,
41+ __func__ , ret , val , mask , expected );
9542}
9643
9744static u32 ufs_renesas_read (struct ufs_hba * hba , u32 reg )
9845{
99- struct ufs_renesas_init_param param = {
100- .mode = MODE_READ ,
101- .reg = reg ,
102- };
103-
104- return ufs_renesas_reg_control (hba , & param );
105- }
106-
107- static void ufs_renesas_wait (struct ufs_hba * hba , u32 delay_us )
108- {
109- struct ufs_renesas_init_param param = {
110- .mode = MODE_WAIT ,
111- .u .delay_us = delay_us ,
112- };
113-
114- ufs_renesas_reg_control (hba , & param );
46+ return ufshcd_readl (hba , reg );
11547}
11648
11749static void ufs_renesas_write (struct ufs_hba * hba , u32 reg , u32 value )
11850{
119- struct ufs_renesas_init_param param = {
120- .mode = MODE_WRITE ,
121- .reg = reg ,
122- .u .val = value ,
123- };
124-
125- ufs_renesas_reg_control (hba , & param );
51+ ufshcd_writel (hba , value , reg );
12652}
12753
12854static void ufs_renesas_write_d0_d4 (struct ufs_hba * hba , u32 data_d0 , u32 data_d4 )
@@ -216,13 +142,13 @@ static void ufs_renesas_pre_init(struct ufs_hba *hba)
216142 /* This setting is for SERIES B */
217143 ufs_renesas_write (hba , 0xc0 , 0x49425308 );
218144 ufs_renesas_write_d0_d4 (hba , 0x00000104 , 0x00000002 );
219- ufs_renesas_wait ( hba , 1 );
145+ udelay ( 1 );
220146 ufs_renesas_write_d0_d4 (hba , 0x00000828 , 0x00000200 );
221- ufs_renesas_wait ( hba , 1 );
147+ udelay ( 1 );
222148 ufs_renesas_write_d0_d4 (hba , 0x00000828 , 0x00000000 );
223149 ufs_renesas_write_d0_d4 (hba , 0x00000104 , 0x00000001 );
224150 ufs_renesas_write_d0_d4 (hba , 0x00000940 , 0x00000001 );
225- ufs_renesas_wait ( hba , 1 );
151+ udelay ( 1 );
226152 ufs_renesas_write_d0_d4 (hba , 0x00000940 , 0x00000000 );
227153
228154 ufs_renesas_write (hba , 0xc0 , 0x49425308 );
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