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70 | 70 | #define PADCFG0_PMODE_SHIFT 10 |
71 | 71 | #define PADCFG0_PMODE_MASK GENMASK(13, 10) |
72 | 72 | #define PADCFG0_PMODE_GPIO 0 |
| 73 | +#define PADCFG0_GPIODIS_SHIFT 8 |
| 74 | +#define PADCFG0_GPIODIS_MASK GENMASK(9, 8) |
| 75 | +#define PADCFG0_GPIODIS_NONE 0 |
| 76 | +#define PADCFG0_GPIODIS_OUTPUT 1 |
| 77 | +#define PADCFG0_GPIODIS_INPUT 2 |
| 78 | +#define PADCFG0_GPIODIS_FULL 3 |
73 | 79 | #define PADCFG0_GPIORXDIS BIT(9) |
74 | 80 | #define PADCFG0_GPIOTXDIS BIT(8) |
75 | 81 | #define PADCFG0_GPIORXSTATE BIT(1) |
@@ -212,7 +218,6 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) |
212 | 218 |
|
213 | 219 | /** |
214 | 220 | * enum - Locking variants of the pad configuration |
215 | | - * |
216 | 221 | * @PAD_UNLOCKED: pad is fully controlled by the configuration registers |
217 | 222 | * @PAD_LOCKED: pad configuration registers, except TX state, are locked |
218 | 223 | * @PAD_LOCKED_TX: pad configuration TX state is locked |
@@ -429,6 +434,36 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, |
429 | 434 | return 0; |
430 | 435 | } |
431 | 436 |
|
| 437 | +/** |
| 438 | + * enum - Possible pad physical connections |
| 439 | + * @PAD_CONNECT_NONE: pad is fully disconnected |
| 440 | + * @PAD_CONNECT_INPUT: pad is in input only mode |
| 441 | + * @PAD_CONNECT_OUTPUT: pad is in output only mode |
| 442 | + * @PAD_CONNECT_FULL: pad is fully connected |
| 443 | + */ |
| 444 | +enum { |
| 445 | + PAD_CONNECT_NONE = 0, |
| 446 | + PAD_CONNECT_INPUT = 1, |
| 447 | + PAD_CONNECT_OUTPUT = 2, |
| 448 | + PAD_CONNECT_FULL = PAD_CONNECT_INPUT | PAD_CONNECT_OUTPUT, |
| 449 | +}; |
| 450 | + |
| 451 | +static int __intel_gpio_get_direction(u32 value) |
| 452 | +{ |
| 453 | + switch ((value & PADCFG0_GPIODIS_MASK) >> PADCFG0_GPIODIS_SHIFT) { |
| 454 | + case PADCFG0_GPIODIS_FULL: |
| 455 | + return PAD_CONNECT_NONE; |
| 456 | + case PADCFG0_GPIODIS_OUTPUT: |
| 457 | + return PAD_CONNECT_INPUT; |
| 458 | + case PADCFG0_GPIODIS_INPUT: |
| 459 | + return PAD_CONNECT_OUTPUT; |
| 460 | + case PADCFG0_GPIODIS_NONE: |
| 461 | + return PAD_CONNECT_FULL; |
| 462 | + default: |
| 463 | + return -ENOTSUPP; |
| 464 | + }; |
| 465 | +} |
| 466 | + |
432 | 467 | static u32 __intel_gpio_set_direction(u32 value, bool input, bool output) |
433 | 468 | { |
434 | 469 | if (input) |
@@ -937,7 +972,7 @@ static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) |
937 | 972 | return -EINVAL; |
938 | 973 |
|
939 | 974 | padcfg0 = readl(reg); |
940 | | - if (!(padcfg0 & PADCFG0_GPIOTXDIS)) |
| 975 | + if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT) |
941 | 976 | return !!(padcfg0 & PADCFG0_GPIOTXSTATE); |
942 | 977 |
|
943 | 978 | return !!(padcfg0 & PADCFG0_GPIORXSTATE); |
@@ -990,10 +1025,10 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
990 | 1025 | if (padcfg0 & PADCFG0_PMODE_MASK) |
991 | 1026 | return -EINVAL; |
992 | 1027 |
|
993 | | - if (padcfg0 & PADCFG0_GPIOTXDIS) |
994 | | - return GPIO_LINE_DIRECTION_IN; |
| 1028 | + if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT) |
| 1029 | + return GPIO_LINE_DIRECTION_OUT; |
995 | 1030 |
|
996 | | - return GPIO_LINE_DIRECTION_OUT; |
| 1031 | + return GPIO_LINE_DIRECTION_IN; |
997 | 1032 | } |
998 | 1033 |
|
999 | 1034 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) |
@@ -1690,7 +1725,8 @@ EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL); |
1690 | 1725 |
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1691 | 1726 | static bool __intel_gpio_is_direct_irq(u32 value) |
1692 | 1727 | { |
1693 | | - return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && |
| 1728 | + return (value & PADCFG0_GPIROUTIOXAPIC) && |
| 1729 | + (__intel_gpio_get_direction(value) == PAD_CONNECT_INPUT) && |
1694 | 1730 | (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO); |
1695 | 1731 | } |
1696 | 1732 |
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