44 */
55
66#include <linux/clk-provider.h>
7+ #include <linux/interconnect-provider.h>
78#include <linux/mod_devicetable.h>
89#include <linux/module.h>
910#include <linux/platform_device.h>
1011#include <linux/regmap.h>
1112
1213#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
14+ #include <dt-bindings/interconnect/qcom,ipq5332.h>
1315
1416#include "clk-alpha-pll.h"
1517#include "clk-branch.h"
@@ -126,17 +128,6 @@ static struct clk_alpha_pll gpll4_main = {
126128 .parent_data = & gcc_parent_data_xo ,
127129 .num_parents = 1 ,
128130 .ops = & clk_alpha_pll_stromer_ops ,
129- /*
130- * There are no consumers for this GPLL in kernel yet,
131- * (will be added soon), so the clock framework
132- * disables this source. But some of the clocks
133- * initialized by boot loaders uses this source. So we
134- * need to keep this clock ON. Add the
135- * CLK_IGNORE_UNUSED flag so the clock will not be
136- * disabled. Once the consumer in kernel is added, we
137- * can get rid of this flag.
138- */
139- .flags = CLK_IGNORE_UNUSED ,
140131 },
141132 },
142133};
@@ -3629,6 +3620,24 @@ static const struct qcom_reset_map gcc_ipq5332_resets[] = {
36293620 [GCC_UNIPHY1_XPCS_ARES ] = { 0x16060 },
36303621};
36313622
3623+ #define IPQ_APPS_ID 5332 /* some unique value */
3624+
3625+ static struct qcom_icc_hws_data icc_ipq5332_hws [] = {
3626+ { MASTER_SNOC_PCIE3_1_M , SLAVE_SNOC_PCIE3_1_M , GCC_SNOC_PCIE3_1LANE_M_CLK },
3627+ { MASTER_ANOC_PCIE3_1_S , SLAVE_ANOC_PCIE3_1_S , GCC_SNOC_PCIE3_1LANE_S_CLK },
3628+ { MASTER_SNOC_PCIE3_2_M , SLAVE_SNOC_PCIE3_2_M , GCC_SNOC_PCIE3_2LANE_M_CLK },
3629+ { MASTER_ANOC_PCIE3_2_S , SLAVE_ANOC_PCIE3_2_S , GCC_SNOC_PCIE3_2LANE_S_CLK },
3630+ { MASTER_SNOC_USB , SLAVE_SNOC_USB , GCC_SNOC_USB_CLK },
3631+ { MASTER_NSSNOC_NSSCC , SLAVE_NSSNOC_NSSCC , GCC_NSSNOC_NSSCC_CLK },
3632+ { MASTER_NSSNOC_SNOC_0 , SLAVE_NSSNOC_SNOC_0 , GCC_NSSNOC_SNOC_CLK },
3633+ { MASTER_NSSNOC_SNOC_1 , SLAVE_NSSNOC_SNOC_1 , GCC_NSSNOC_SNOC_1_CLK },
3634+ { MASTER_NSSNOC_ATB , SLAVE_NSSNOC_ATB , GCC_NSSNOC_ATB_CLK },
3635+ { MASTER_NSSNOC_PCNOC_1 , SLAVE_NSSNOC_PCNOC_1 , GCC_NSSNOC_PCNOC_1_CLK },
3636+ { MASTER_NSSNOC_QOSGEN_REF , SLAVE_NSSNOC_QOSGEN_REF , GCC_NSSNOC_QOSGEN_REF_CLK },
3637+ { MASTER_NSSNOC_TIMEOUT_REF , SLAVE_NSSNOC_TIMEOUT_REF , GCC_NSSNOC_TIMEOUT_REF_CLK },
3638+ { MASTER_NSSNOC_XO_DCD , SLAVE_NSSNOC_XO_DCD , GCC_NSSNOC_XO_DCD_CLK },
3639+ };
3640+
36323641static const struct regmap_config gcc_ipq5332_regmap_config = {
36333642 .reg_bits = 32 ,
36343643 .reg_stride = 4 ,
@@ -3657,6 +3666,9 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = {
36573666 .num_resets = ARRAY_SIZE (gcc_ipq5332_resets ),
36583667 .clk_hws = gcc_ipq5332_hws ,
36593668 .num_clk_hws = ARRAY_SIZE (gcc_ipq5332_hws ),
3669+ .icc_hws = icc_ipq5332_hws ,
3670+ .num_icc_hws = ARRAY_SIZE (icc_ipq5332_hws ),
3671+ .icc_first_node_id = IPQ_APPS_ID ,
36603672};
36613673
36623674static int gcc_ipq5332_probe (struct platform_device * pdev )
@@ -3675,6 +3687,7 @@ static struct platform_driver gcc_ipq5332_driver = {
36753687 .driver = {
36763688 .name = "gcc-ipq5332" ,
36773689 .of_match_table = gcc_ipq5332_match_table ,
3690+ .sync_state = icc_sync_state ,
36783691 },
36793692};
36803693
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