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author
Linus Walleij
committed
Merge tag 'renesas-pinctrl-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.14 (take two) - Add support for alpha-numerical port references on the RZ/V2H SoC, - Add support for the RZ/G3E (R9A09G047) Soc. Signed-off-by: Linus Walleij <[email protected]>
2 parents cef4f1b + 829356d commit 94467a2

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‎Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,19 +4,22 @@
44
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

7-
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
7+
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
88

99
maintainers:
1010
- Lad Prabhakar <[email protected]>
1111

1212
description:
13-
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
14-
and control of clock signals for the IP modules, generation and control of resets,
15-
and control over booting, low power consumption and power supply domains.
13+
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
14+
generation and control of clock signals for the IP modules, generation and
15+
control of resets, and control over booting, low power consumption and power
16+
supply domains.
1617

1718
properties:
1819
compatible:
19-
const: renesas,r9a09g057-cpg
20+
enum:
21+
- renesas,r9a09g047-cpg # RZ/G3E
22+
- renesas,r9a09g057-cpg # RZ/V2H
2023

2124
reg:
2225
maxItems: 1
@@ -37,7 +40,7 @@ properties:
3740
description: |
3841
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
3942
and a core clock reference, as defined in
40-
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
43+
<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
4144
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
4245
a module number. The module number is calculated as the CLKON register
4346
offset index multiplied by 16, plus the actual bit in the register

‎Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ properties:
2626
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
2727
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
2828
- renesas,r9a08g045-pinctrl # RZ/G3S
29+
- renesas,r9a09g047-pinctrl # RZ/G3E
2930
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
3031

3132
- items:
@@ -125,7 +126,7 @@ additionalProperties:
125126
drive-push-pull: true
126127
renesas,output-impedance:
127128
description:
128-
Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
129+
Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
129130
property corresponds to register bit values that can be set in the PFC_IOLH_mn
130131
register, which adjusts the drive strength value and is pin-dependent.
131132
$ref: /schemas/types.yaml#/definitions/uint32
@@ -142,7 +143,9 @@ allOf:
142143
properties:
143144
compatible:
144145
contains:
145-
const: renesas,r9a09g057-pinctrl
146+
enum:
147+
- renesas,r9a09g047-pinctrl
148+
- renesas,r9a09g057-pinctrl
146149
then:
147150
properties:
148151
resets:

‎Documentation/devicetree/bindings/soc/renesas/renesas.yaml‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -525,6 +525,23 @@ properties:
525525
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
526526
- const: renesas,r9a09g011
527527

528+
- description: RZ/G3E (R9A09G047)
529+
items:
530+
- enum:
531+
- renesas,smarc2-evk # RZ SMARC Carrier-II EVK
532+
- enum:
533+
- renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
534+
- enum:
535+
- renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
536+
- renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
537+
- renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
538+
- renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
539+
- renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
540+
- renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
541+
- renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
542+
- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
543+
- const: renesas,r9a09g047
544+
528545
- description: RZ/V2H(P) (R9A09G057)
529546
items:
530547
- enum:

‎drivers/pinctrl/renesas/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ config PINCTRL_RENESAS
4141
select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0
4242
select PINCTRL_RZG2L if ARCH_RZG2L
4343
select PINCTRL_RZV2M if ARCH_R9A09G011
44+
select PINCTRL_RZG2L if ARCH_R9A09G047
4445
select PINCTRL_RZG2L if ARCH_R9A09G057
4546
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
4647
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

‎drivers/pinctrl/renesas/pinctrl-rzg2l.c‎

Lines changed: 180 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,8 @@
2626
#include <linux/pinctrl/pinctrl.h>
2727
#include <linux/pinctrl/pinmux.h>
2828

29+
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
30+
#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
2931
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
3032

3133
#include "../core.h"
@@ -381,13 +383,51 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
381383
return 0;
382384
}
383385

386+
static const u64 r9a09g047_variable_pin_cfg[] = {
387+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
388+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),
389+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS),
390+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS),
391+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS),
392+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
393+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
394+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
395+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
396+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
397+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
398+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS),
399+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS),
400+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
401+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
402+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
403+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
404+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
405+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
406+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
407+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
408+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
409+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS),
410+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS),
411+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS),
412+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
413+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
414+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
415+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
416+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
417+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
418+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS),
419+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
420+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
421+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
422+
};
423+
384424
static const u64 r9a09g057_variable_pin_cfg[] = {
385-
RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),
386-
RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
387-
RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
388-
RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
389-
RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
390-
RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
425+
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
426+
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
427+
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
428+
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
429+
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
430+
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
391431
};
392432

393433
#ifdef CONFIG_RISCV
@@ -1962,6 +2002,73 @@ static const u64 r9a08g045_gpio_configs[] = {
19622002
RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
19632003
};
19642004

2005+
static const char * const rzg3e_gpio_names[] = {
2006+
"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
2007+
"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
2008+
"P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
2009+
"P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
2010+
"P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
2011+
"P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
2012+
"P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
2013+
"P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
2014+
"P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
2015+
"", "", "", "", "", "", "", "",
2016+
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
2017+
"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
2018+
"PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
2019+
"PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
2020+
"PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
2021+
"PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
2022+
"PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
2023+
"PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
2024+
"", "", "", "", "", "", "", "",
2025+
"PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
2026+
"PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
2027+
"PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
2028+
"PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
2029+
"", "", "", "", "", "", "", "",
2030+
"", "", "", "", "", "", "", "",
2031+
"", "", "", "", "", "", "", "",
2032+
"", "", "", "", "", "", "", "",
2033+
"", "", "", "", "", "", "", "",
2034+
"PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
2035+
};
2036+
2037+
static const u64 r9a09g047_gpio_configs[] = {
2038+
RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
2039+
RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS |
2040+
PIN_CFG_ELC), /* P1 */
2041+
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
2042+
PIN_CFG_NOD), /* P2 */
2043+
RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
2044+
RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
2045+
RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
2046+
RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */
2047+
RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS |
2048+
PIN_CFG_ELC), /* P7 */
2049+
RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */
2050+
0x0,
2051+
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
2052+
RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */
2053+
RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */
2054+
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
2055+
RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */
2056+
RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */
2057+
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
2058+
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
2059+
0x0,
2060+
RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
2061+
RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */
2062+
RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */
2063+
RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */
2064+
0x0,
2065+
0x0,
2066+
0x0,
2067+
0x0,
2068+
0x0,
2069+
RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */
2070+
};
2071+
19652072
static const char * const rzv2h_gpio_names[] = {
19662073
"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
19672074
"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
@@ -2252,6 +2359,43 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
22522359
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
22532360
};
22542361

2362+
static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
2363+
{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0,
2364+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
2365+
{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1,
2366+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
2367+
{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,
2368+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
2369+
{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
2370+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
2371+
{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0,
2372+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2373+
{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
2374+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2375+
{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2,
2376+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2377+
{ "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3,
2378+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2379+
{ "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4,
2380+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2381+
{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0,
2382+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2383+
{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1,
2384+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2385+
{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2,
2386+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2387+
{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3,
2388+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2389+
{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4,
2390+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2391+
{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5,
2392+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2393+
{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6,
2394+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2395+
{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7,
2396+
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2397+
};
2398+
22552399
static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
22562400
{
22572401
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
@@ -2762,6 +2906,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
27622906
BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
27632907
ARRAY_SIZE(rzg2l_gpio_names));
27642908

2909+
BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >
2910+
ARRAY_SIZE(rzg3e_gpio_names));
2911+
27652912
BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
27662913
ARRAY_SIZE(rzv2h_gpio_names));
27672914

@@ -3160,6 +3307,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
31603307
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
31613308
};
31623309

3310+
static struct rzg2l_pinctrl_data r9a09g047_data = {
3311+
.port_pins = rzg3e_gpio_names,
3312+
.port_pin_configs = r9a09g047_gpio_configs,
3313+
.n_ports = ARRAY_SIZE(r9a09g047_gpio_configs),
3314+
.dedicated_pins = rzg3e_dedicated_pins,
3315+
.n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
3316+
.n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
3317+
.hwcfg = &rzv2h_hwcfg,
3318+
.variable_pin_cfg = r9a09g047_variable_pin_cfg,
3319+
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
3320+
.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3321+
.custom_params = renesas_rzv2h_custom_bindings,
3322+
#ifdef CONFIG_DEBUG_FS
3323+
.custom_conf_items = renesas_rzv2h_conf_items,
3324+
#endif
3325+
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3326+
.pmc_writeb = &rzv2h_pmc_writeb,
3327+
.oen_read = &rzv2h_oen_read,
3328+
.oen_write = &rzv2h_oen_write,
3329+
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
3330+
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
3331+
};
3332+
31633333
static struct rzg2l_pinctrl_data r9a09g057_data = {
31643334
.port_pins = rzv2h_gpio_names,
31653335
.port_pin_configs = r9a09g057_gpio_configs,
@@ -3196,6 +3366,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
31963366
.compatible = "renesas,r9a08g045-pinctrl",
31973367
.data = &r9a08g045_data,
31983368
},
3369+
{
3370+
.compatible = "renesas,r9a09g047-pinctrl",
3371+
.data = &r9a09g047_data,
3372+
},
31993373
{
32003374
.compatible = "renesas,r9a09g057-pinctrl",
32013375
.data = &r9a09g057_data,

‎include/dt-bindings/clock/renesas,r9a09g047-cpg.h‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
*
3+
* Copyright (C) 2024 Renesas Electronics Corp.
4+
*/
5+
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
6+
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
7+
8+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
9+
10+
/* Core Clock list */
11+
#define R9A09G047_SYS_0_PCLK 0
12+
#define R9A09G047_CA55_0_CORECLK0 1
13+
#define R9A09G047_CA55_0_CORECLK1 2
14+
#define R9A09G047_CA55_0_CORECLK2 3
15+
#define R9A09G047_CA55_0_CORECLK3 4
16+
#define R9A09G047_CA55_0_PERIPHCLK 5
17+
#define R9A09G047_CM33_CLK0 6
18+
#define R9A09G047_CST_0_SWCLKTCK 7
19+
#define R9A09G047_IOTOP_0_SHCLK 8
20+
21+
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */

‎include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+
/*
3+
* This header provides constants for Renesas RZ/G3E family pinctrl bindings.
4+
*
5+
* Copyright (C) 2024 Renesas Electronics Corp.
6+
*
7+
*/
8+
9+
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
10+
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
11+
12+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
13+
14+
/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */
15+
#define RZG3E_P0 0
16+
#define RZG3E_P1 1
17+
#define RZG3E_P2 2
18+
#define RZG3E_P3 3
19+
#define RZG3E_P4 4
20+
#define RZG3E_P5 5
21+
#define RZG3E_P6 6
22+
#define RZG3E_P7 7
23+
#define RZG3E_P8 8
24+
#define RZG3E_PA 10
25+
#define RZG3E_PB 11
26+
#define RZG3E_PC 12
27+
#define RZG3E_PD 13
28+
#define RZG3E_PE 14
29+
#define RZG3E_PF 15
30+
#define RZG3E_PG 16
31+
#define RZG3E_PH 17
32+
#define RZG3E_PJ 19
33+
#define RZG3E_PK 20
34+
#define RZG3E_PL 21
35+
#define RZG3E_PM 22
36+
#define RZG3E_PS 28
37+
38+
#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
39+
#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin)
40+
41+
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */

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