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Paolo Abeni
committed
Merge branch 'arrange-pse-core-and-update-tps23881-driver'
Kory Maincent says: ==================== Arrange PSE core and update TPS23881 driver This patch includes several improvements to the PSE core for better implementation and maintainability: - Move the conversion between current limit and power limit from the driver to the PSE core. - Update power and current limit checks. - Split the ethtool_get_status callback into multiple callbacks. - Fix PSE PI of_node detection. - Clean ethtool header of PSE structures. Additionally, the TPS23881 driver has been updated to support power limit and measurement features, aligning with the new PSE core functionalities. This patch series is the first part of the budget evaluation strategy support patch series sent earlier: https://lore.kernel.org/netdev/20250104161622.7b82dfdf@kmaincent-XPS-13-7390/T/#t Signed-off-by: Kory Maincent <[email protected]> ==================== Link: https://patch.msgid.link/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
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‎drivers/net/pse-pd/pd692x0.c‎

Lines changed: 119 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -431,31 +431,6 @@ static int pd692x0_pi_disable(struct pse_controller_dev *pcdev, int id)
431431
return 0;
432432
}
433433

434-
static int pd692x0_pi_is_enabled(struct pse_controller_dev *pcdev, int id)
435-
{
436-
struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
437-
struct pd692x0_msg msg, buf = {0};
438-
int ret;
439-
440-
ret = pd692x0_fw_unavailable(priv);
441-
if (ret)
442-
return ret;
443-
444-
msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
445-
msg.sub[2] = id;
446-
ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
447-
if (ret < 0)
448-
return ret;
449-
450-
if (buf.sub[1]) {
451-
priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
452-
return 1;
453-
} else {
454-
priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
455-
return 0;
456-
}
457-
}
458-
459434
struct pd692x0_pse_ext_state_mapping {
460435
u32 status_code;
461436
enum ethtool_c33_pse_ext_state pse_ext_state;
@@ -517,21 +492,38 @@ pd692x0_pse_ext_state_map[] = {
517492
{ /* sentinel */ }
518493
};
519494

520-
static void
521-
pd692x0_get_ext_state(struct ethtool_c33_pse_ext_state_info *c33_ext_state_info,
522-
u32 status_code)
495+
static int
496+
pd692x0_pi_get_ext_state(struct pse_controller_dev *pcdev, int id,
497+
struct pse_ext_state_info *ext_state_info)
523498
{
499+
struct ethtool_c33_pse_ext_state_info *c33_ext_state_info;
524500
const struct pd692x0_pse_ext_state_mapping *ext_state_map;
501+
struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
502+
struct pd692x0_msg msg, buf = {0};
503+
int ret;
525504

505+
ret = pd692x0_fw_unavailable(priv);
506+
if (ret)
507+
return ret;
508+
509+
msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
510+
msg.sub[2] = id;
511+
ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
512+
if (ret < 0)
513+
return ret;
514+
515+
c33_ext_state_info = &ext_state_info->c33_ext_state_info;
526516
ext_state_map = pd692x0_pse_ext_state_map;
527517
while (ext_state_map->status_code) {
528-
if (ext_state_map->status_code == status_code) {
518+
if (ext_state_map->status_code == buf.sub[0]) {
529519
c33_ext_state_info->c33_pse_ext_state = ext_state_map->pse_ext_state;
530520
c33_ext_state_info->__c33_pse_ext_substate = ext_state_map->pse_ext_substate;
531-
return;
521+
return 0;
532522
}
533523
ext_state_map++;
534524
}
525+
526+
return 0;
535527
}
536528

537529
struct pd692x0_class_pw {
@@ -613,35 +605,36 @@ static int pd692x0_pi_set_pw_from_table(struct device *dev,
613605
}
614606

615607
static int
616-
pd692x0_pi_get_pw_ranges(struct pse_control_status *st)
608+
pd692x0_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id,
609+
struct pse_pw_limit_ranges *pw_limit_ranges)
617610
{
611+
struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
618612
const struct pd692x0_class_pw *pw_table;
619613
int i;
620614

621615
pw_table = pd692x0_class_pw_table;
622-
st->c33_pw_limit_ranges = kcalloc(PD692X0_CLASS_PW_TABLE_SIZE,
623-
sizeof(struct ethtool_c33_pse_pw_limit_range),
624-
GFP_KERNEL);
625-
if (!st->c33_pw_limit_ranges)
616+
c33_pw_limit_ranges = kcalloc(PD692X0_CLASS_PW_TABLE_SIZE,
617+
sizeof(*c33_pw_limit_ranges),
618+
GFP_KERNEL);
619+
if (!c33_pw_limit_ranges)
626620
return -ENOMEM;
627621

628622
for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
629-
st->c33_pw_limit_ranges[i].min = pw_table->class_pw;
630-
st->c33_pw_limit_ranges[i].max = pw_table->class_pw + pw_table->max_added_class_pw;
623+
c33_pw_limit_ranges[i].min = pw_table->class_pw;
624+
c33_pw_limit_ranges[i].max = pw_table->class_pw +
625+
pw_table->max_added_class_pw;
631626
}
632627

633-
st->c33_pw_limit_nb_ranges = i;
634-
return 0;
628+
pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges;
629+
return i;
635630
}
636631

637-
static int pd692x0_ethtool_get_status(struct pse_controller_dev *pcdev,
638-
unsigned long id,
639-
struct netlink_ext_ack *extack,
640-
struct pse_control_status *status)
632+
static int
633+
pd692x0_pi_get_admin_state(struct pse_controller_dev *pcdev, int id,
634+
struct pse_admin_state *admin_state)
641635
{
642636
struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
643637
struct pd692x0_msg msg, buf = {0};
644-
u32 class;
645638
int ret;
646639

647640
ret = pd692x0_fw_unavailable(priv);
@@ -654,39 +647,65 @@ static int pd692x0_ethtool_get_status(struct pse_controller_dev *pcdev,
654647
if (ret < 0)
655648
return ret;
656649

657-
/* Compare Port Status (Communication Protocol Document par. 7.1) */
658-
if ((buf.sub[0] & 0xf0) == 0x80 || (buf.sub[0] & 0xf0) == 0x90)
659-
status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING;
660-
else if (buf.sub[0] == 0x1b || buf.sub[0] == 0x22)
661-
status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING;
662-
else if (buf.sub[0] == 0x12)
663-
status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_FAULT;
664-
else
665-
status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED;
666-
667650
if (buf.sub[1])
668-
status->c33_admin_state = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
651+
admin_state->c33_admin_state =
652+
ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
669653
else
670-
status->c33_admin_state = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
654+
admin_state->c33_admin_state =
655+
ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
671656

672-
priv->admin_state[id] = status->c33_admin_state;
657+
priv->admin_state[id] = admin_state->c33_admin_state;
673658

674-
pd692x0_get_ext_state(&status->c33_ext_state_info, buf.sub[0]);
675-
status->c33_actual_pw = (buf.data[0] << 4 | buf.data[1]) * 100;
659+
return 0;
660+
}
676661

677-
msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM];
662+
static int
663+
pd692x0_pi_get_pw_status(struct pse_controller_dev *pcdev, int id,
664+
struct pse_pw_status *pw_status)
665+
{
666+
struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
667+
struct pd692x0_msg msg, buf = {0};
668+
int ret;
669+
670+
ret = pd692x0_fw_unavailable(priv);
671+
if (ret)
672+
return ret;
673+
674+
msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
678675
msg.sub[2] = id;
679-
memset(&buf, 0, sizeof(buf));
680676
ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
681677
if (ret < 0)
682678
return ret;
683679

684-
ret = pd692x0_pi_get_pw_from_table(buf.data[0], buf.data[1]);
685-
if (ret < 0)
680+
/* Compare Port Status (Communication Protocol Document par. 7.1) */
681+
if ((buf.sub[0] & 0xf0) == 0x80 || (buf.sub[0] & 0xf0) == 0x90)
682+
pw_status->c33_pw_status =
683+
ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING;
684+
else if (buf.sub[0] == 0x1b || buf.sub[0] == 0x22)
685+
pw_status->c33_pw_status =
686+
ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING;
687+
else if (buf.sub[0] == 0x12)
688+
pw_status->c33_pw_status =
689+
ETHTOOL_C33_PSE_PW_D_STATUS_FAULT;
690+
else
691+
pw_status->c33_pw_status =
692+
ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED;
693+
694+
return 0;
695+
}
696+
697+
static int
698+
pd692x0_pi_get_pw_class(struct pse_controller_dev *pcdev, int id)
699+
{
700+
struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
701+
struct pd692x0_msg msg, buf = {0};
702+
u32 class;
703+
int ret;
704+
705+
ret = pd692x0_fw_unavailable(priv);
706+
if (ret)
686707
return ret;
687-
status->c33_avail_pw_limit = ret;
688708

689-
memset(&buf, 0, sizeof(buf));
690709
msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_CLASS];
691710
msg.sub[2] = id;
692711
ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
@@ -695,13 +714,29 @@ static int pd692x0_ethtool_get_status(struct pse_controller_dev *pcdev,
695714

696715
class = buf.data[3] >> 4;
697716
if (class <= 8)
698-
status->c33_pw_class = class;
717+
return class;
699718

700-
ret = pd692x0_pi_get_pw_ranges(status);
719+
return 0;
720+
}
721+
722+
static int
723+
pd692x0_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id)
724+
{
725+
struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
726+
struct pd692x0_msg msg, buf = {0};
727+
int ret;
728+
729+
ret = pd692x0_fw_unavailable(priv);
730+
if (ret)
731+
return ret;
732+
733+
msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
734+
msg.sub[2] = id;
735+
ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
701736
if (ret < 0)
702737
return ret;
703738

704-
return 0;
739+
return (buf.data[0] << 4 | buf.data[1]) * 100;
705740
}
706741

707742
static struct pd692x0_msg_ver pd692x0_get_sw_version(struct pd692x0_priv *priv)
@@ -999,62 +1034,37 @@ static int pd692x0_pi_get_voltage(struct pse_controller_dev *pcdev, int id)
9991034
return (buf.sub[0] << 8 | buf.sub[1]) * 100000;
10001035
}
10011036

1002-
static int pd692x0_pi_get_current_limit(struct pse_controller_dev *pcdev,
1003-
int id)
1037+
static int pd692x0_pi_get_pw_limit(struct pse_controller_dev *pcdev,
1038+
int id)
10041039
{
10051040
struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
10061041
struct pd692x0_msg msg, buf = {0};
1007-
int mW, uV, uA, ret;
1008-
s64 tmp_64;
1042+
int ret;
10091043

10101044
msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM];
10111045
msg.sub[2] = id;
10121046
ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
10131047
if (ret < 0)
10141048
return ret;
10151049

1016-
ret = pd692x0_pi_get_pw_from_table(buf.data[2], buf.data[3]);
1017-
if (ret < 0)
1018-
return ret;
1019-
mW = ret;
1020-
1021-
ret = pd692x0_pi_get_voltage(pcdev, id);
1022-
if (ret < 0)
1023-
return ret;
1024-
uV = ret;
1025-
1026-
tmp_64 = mW;
1027-
tmp_64 *= 1000000000ull;
1028-
/* uA = mW * 1000000000 / uV */
1029-
uA = DIV_ROUND_CLOSEST_ULL(tmp_64, uV);
1030-
return uA;
1050+
return pd692x0_pi_get_pw_from_table(buf.data[2], buf.data[3]);
10311051
}
10321052

1033-
static int pd692x0_pi_set_current_limit(struct pse_controller_dev *pcdev,
1034-
int id, int max_uA)
1053+
static int pd692x0_pi_set_pw_limit(struct pse_controller_dev *pcdev,
1054+
int id, int max_mW)
10351055
{
10361056
struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
10371057
struct device *dev = &priv->client->dev;
10381058
struct pd692x0_msg msg, buf = {0};
1039-
int uV, ret, mW;
1040-
s64 tmp_64;
1059+
int ret;
10411060

10421061
ret = pd692x0_fw_unavailable(priv);
10431062
if (ret)
10441063
return ret;
10451064

1046-
ret = pd692x0_pi_get_voltage(pcdev, id);
1047-
if (ret < 0)
1048-
return ret;
1049-
uV = ret;
1050-
10511065
msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
10521066
msg.sub[2] = id;
1053-
tmp_64 = uV;
1054-
tmp_64 *= max_uA;
1055-
/* mW = uV * uA / 1000000000 */
1056-
mW = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000);
1057-
ret = pd692x0_pi_set_pw_from_table(dev, &msg, mW);
1067+
ret = pd692x0_pi_set_pw_from_table(dev, &msg, max_mW);
10581068
if (ret)
10591069
return ret;
10601070

@@ -1063,13 +1073,17 @@ static int pd692x0_pi_set_current_limit(struct pse_controller_dev *pcdev,
10631073

10641074
static const struct pse_controller_ops pd692x0_ops = {
10651075
.setup_pi_matrix = pd692x0_setup_pi_matrix,
1066-
.ethtool_get_status = pd692x0_ethtool_get_status,
1076+
.pi_get_admin_state = pd692x0_pi_get_admin_state,
1077+
.pi_get_pw_status = pd692x0_pi_get_pw_status,
1078+
.pi_get_ext_state = pd692x0_pi_get_ext_state,
1079+
.pi_get_pw_class = pd692x0_pi_get_pw_class,
1080+
.pi_get_actual_pw = pd692x0_pi_get_actual_pw,
10671081
.pi_enable = pd692x0_pi_enable,
10681082
.pi_disable = pd692x0_pi_disable,
1069-
.pi_is_enabled = pd692x0_pi_is_enabled,
10701083
.pi_get_voltage = pd692x0_pi_get_voltage,
1071-
.pi_get_current_limit = pd692x0_pi_get_current_limit,
1072-
.pi_set_current_limit = pd692x0_pi_set_current_limit,
1084+
.pi_get_pw_limit = pd692x0_pi_get_pw_limit,
1085+
.pi_set_pw_limit = pd692x0_pi_set_pw_limit,
1086+
.pi_get_pw_limit_ranges = pd692x0_pi_get_pw_limit_ranges,
10731087
};
10741088

10751089
#define PD692X0_FW_LINE_MAX_SZ 0xff

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