drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code

Drop all the local variables for the DPLL dividers for vlv/chv
and just consult the state directly.

Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jani Nikula <[email protected]>

Author: vsyrjala

drivers/gpu/drm/i915/display/intel_dpll.c

@@ -1899,20 +1899,13 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	enum pipe pipe = crtc->pipe;
-	u32 mdiv;
-	u32 bestn, bestm1, bestm2, bestp1, bestp2;
-	u32 coreclk, reg_val;
+	u32 mdiv, coreclk, reg_val;
 
 	vlv_dpio_get(dev_priv);
 
-	bestn = crtc_state->dpll.n;
-	bestm1 = crtc_state->dpll.m1;
-	bestm2 = crtc_state->dpll.m2;
-	bestp1 = crtc_state->dpll.p1;
-	bestp2 = crtc_state->dpll.p2;
-
 	/* See eDP HDMI DPIO driver vbios notes doc */
 
 	/* PLL B needs special handling */
@@ -1931,10 +1924,12 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
 
 	/* Set idtafcrecal before PLL is enabled */
-	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
-	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
-	mdiv |= ((bestn << DPIO_N_SHIFT));
-	mdiv |= (1 << DPIO_K_SHIFT);
+	mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
+		(clock->m2 & DPIO_M2DIV_MASK) |
+		(clock->p1 << DPIO_P1_SHIFT) |
+		(clock->p2 << DPIO_P2_SHIFT) |
+		(clock->n << DPIO_N_SHIFT) |
+		(1 << DPIO_K_SHIFT);
 
 	/*
 	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
@@ -2030,47 +2025,44 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	enum pipe pipe = crtc->pipe;
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
-	u32 loopfilter, tribuf_calcntr;
-	u32 bestm2, bestp1, bestp2, bestm2_frac;
-	u32 dpio_val;
-	int vco;
-
-	bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;
-	bestm2 = crtc_state->dpll.m2 >> 22;
-	bestp1 = crtc_state->dpll.p1;
-	bestp2 = crtc_state->dpll.p2;
-	vco = crtc_state->dpll.vco;
+	u32 dpio_val, loopfilter, tribuf_calcntr;
+	u32 m2_frac;
+
+	m2_frac = clock->m2 & 0x3fffff;
 	dpio_val = 0;
 	loopfilter = 0;
 
 	vlv_dpio_get(dev_priv);
 
 	/* p1 and p2 divider */
 	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
-			5 << DPIO_CHV_S1_DIV_SHIFT |
-			bestp1 << DPIO_CHV_P1_DIV_SHIFT |
-			bestp2 << DPIO_CHV_P2_DIV_SHIFT |
-			1 << DPIO_CHV_K_DIV_SHIFT);
+		       5 << DPIO_CHV_S1_DIV_SHIFT |
+		       clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
+		       clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
+		       1 << DPIO_CHV_K_DIV_SHIFT);
 
 	/* Feedback post-divider - m2 */
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port),
+		       clock->m2 >> 22);
 
 	/* Feedback refclk divider - n and m1 */
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
-			DPIO_CHV_M1_DIV_BY_2 |
-			1 << DPIO_CHV_N_DIV_SHIFT);
+		       DPIO_CHV_M1_DIV_BY_2 |
+		       1 << DPIO_CHV_N_DIV_SHIFT);
 
 	/* M2 fraction division */
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port),
+		       m2_frac);
 
 	/* M2 fraction division enable */
 	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
 	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
 	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
-	if (bestm2_frac)
+	if (m2_frac)
 		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val);
 
@@ -2079,22 +2071,22 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
 					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
 	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
-	if (!bestm2_frac)
+	if (!m2_frac)
 		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val);
 
 	/* Loop filter */
-	if (vco == 5400000) {
+	if (clock->vco == 5400000) {
 		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
 		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
 		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
 		tribuf_calcntr = 0x9;
-	} else if (vco <= 6200000) {
+	} else if (clock->vco <= 6200000) {
 		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
 		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
 		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
 		tribuf_calcntr = 0x9;
-	} else if (vco <= 6480000) {
+	} else if (clock->vco <= 6480000) {
 		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
 		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
 		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);