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80 | 80 | #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) |
81 | 81 | #define MSGF_MISC_SR_FATAL_DEV BIT(23) |
82 | 82 | #define MSGF_MISC_SR_LINK_DOWN BIT(24) |
83 | | -#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) |
84 | | -#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) |
| 83 | +#define MSGF_MISC_SR_LINK_AUTO_BWIDTH BIT(25) |
| 84 | +#define MSGF_MISC_SR_LINK_BWIDTH BIT(26) |
85 | 85 |
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86 | 86 | #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ |
87 | 87 | MSGF_MISC_SR_RXMSG_OVER | \ |
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96 | 96 | MSGF_MISC_SR_NON_FATAL_DEV | \ |
97 | 97 | MSGF_MISC_SR_FATAL_DEV | \ |
98 | 98 | MSGF_MISC_SR_LINK_DOWN | \ |
99 | | - MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ |
100 | | - MSGF_MSIC_SR_LINK_BWIDTH) |
| 99 | + MSGF_MISC_SR_LINK_AUTO_BWIDTH | \ |
| 100 | + MSGF_MISC_SR_LINK_BWIDTH) |
101 | 101 |
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102 | 102 | /* Legacy interrupt status mask bits */ |
103 | 103 | #define MSGF_LEG_SR_INTA BIT(0) |
@@ -299,10 +299,10 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) |
299 | 299 | if (misc_stat & MSGF_MISC_SR_FATAL_DEV) |
300 | 300 | dev_err(dev, "Fatal Error Detected\n"); |
301 | 301 |
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302 | | - if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) |
| 302 | + if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH) |
303 | 303 | dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n"); |
304 | 304 |
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305 | | - if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) |
| 305 | + if (misc_stat & MSGF_MISC_SR_LINK_BWIDTH) |
306 | 306 | dev_info(dev, "Link Bandwidth Management Status bit set\n"); |
307 | 307 |
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308 | 308 | /* Clear misc interrupt status */ |
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