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lhanlyuBartosz Golaszewski
lhanlyu
authored and
Bartosz Golaszewski
committed
gpio: mpfs: add polarfire soc gpio support
Add a driver to support the Polarfire SoC gpio controller. Interrupt controller support is unavailable for now and will be added at a later date. Signed-off-by: Lewis Hanly <[email protected]> Co-developed-by: Conor Dooley <[email protected]> Signed-off-by: Conor Dooley <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Link: https://lore.kernel.org/r/20241104-tiny-evaluate-9336020b4b6a@spud Signed-off-by: Bartosz Golaszewski <[email protected]>
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‎drivers/gpio/Kconfig‎

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@@ -544,6 +544,12 @@ config GPIO_PL061
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help
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Say yes here to support the PrimeCell PL061 GPIO device.
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config GPIO_POLARFIRE_SOC
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bool "Microchip FPGA GPIO support"
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select REGMAP_MMIO
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help
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Say yes here to support the GPIO controllers on Microchip FPGAs.
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config GPIO_PXA
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bool "PXA GPIO support"
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depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST

‎drivers/gpio/Makefile‎

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@@ -135,6 +135,7 @@ obj-$(CONFIG_GPIO_PCI_IDIO_16) += gpio-pci-idio-16.o
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obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o
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obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
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obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
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obj-$(CONFIG_GPIO_POLARFIRE_SOC) += gpio-mpfs.o
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obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
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obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
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obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o

‎drivers/gpio/gpio-mpfs.c‎

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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* Microchip PolarFire SoC (MPFS) GPIO controller driver
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*
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* Copyright (c) 2018-2024 Microchip Technology Inc. and its subsidiaries
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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#define MPFS_GPIO_CTRL(i) (0x4 * (i))
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#define MPFS_MAX_NUM_GPIO 32
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#define MPFS_GPIO_EN_INT 3
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#define MPFS_GPIO_EN_OUT_BUF BIT(2)
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#define MPFS_GPIO_EN_IN BIT(1)
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#define MPFS_GPIO_EN_OUT BIT(0)
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#define MPFS_GPIO_DIR_MASK GENMASK(2, 0)
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#define MPFS_GPIO_TYPE_INT_EDGE_BOTH 0x80
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#define MPFS_GPIO_TYPE_INT_EDGE_NEG 0x60
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#define MPFS_GPIO_TYPE_INT_EDGE_POS 0x40
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#define MPFS_GPIO_TYPE_INT_LEVEL_LOW 0x20
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#define MPFS_GPIO_TYPE_INT_LEVEL_HIGH 0x00
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#define MPFS_GPIO_TYPE_INT_MASK GENMASK(7, 5)
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#define MPFS_IRQ_REG 0x80
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#define MPFS_INP_REG 0x84
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#define MPFS_OUTP_REG 0x88
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struct mpfs_gpio_chip {
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struct regmap *regs;
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struct gpio_chip gc;
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};
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static const struct regmap_config mpfs_gpio_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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static int mpfs_gpio_direction_input(struct gpio_chip *gc, unsigned int gpio_index)
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{
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struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
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regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index),
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MPFS_GPIO_DIR_MASK, MPFS_GPIO_EN_IN);
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return 0;
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}
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static int mpfs_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio_index, int value)
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{
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struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
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regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index),
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MPFS_GPIO_DIR_MASK, MPFS_GPIO_EN_IN);
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regmap_update_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index),
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value << gpio_index);
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return 0;
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}
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static int mpfs_gpio_get_direction(struct gpio_chip *gc,
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unsigned int gpio_index)
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{
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struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
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unsigned int gpio_cfg;
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regmap_read(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), &gpio_cfg);
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if (gpio_cfg & MPFS_GPIO_EN_IN)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int mpfs_gpio_get(struct gpio_chip *gc, unsigned int gpio_index)
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{
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struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
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if (mpfs_gpio_get_direction(gc, gpio_index) == GPIO_LINE_DIRECTION_OUT)
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return regmap_test_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index));
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else
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return regmap_test_bits(mpfs_gpio->regs, MPFS_INP_REG, BIT(gpio_index));
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}
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static void mpfs_gpio_set(struct gpio_chip *gc, unsigned int gpio_index, int value)
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{
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struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
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mpfs_gpio_get(gc, gpio_index);
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regmap_update_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index),
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value << gpio_index);
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mpfs_gpio_get(gc, gpio_index);
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}
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static int mpfs_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mpfs_gpio_chip *mpfs_gpio;
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struct clk *clk;
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void __iomem *base;
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int ngpios;
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mpfs_gpio = devm_kzalloc(dev, sizeof(*mpfs_gpio), GFP_KERNEL);
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if (!mpfs_gpio)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return dev_err_probe(dev, PTR_ERR(base), "failed to ioremap memory resource\n");
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mpfs_gpio->regs = devm_regmap_init_mmio(dev, base, &mpfs_gpio_regmap_config);
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if (IS_ERR(mpfs_gpio->regs))
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return dev_err_probe(dev, PTR_ERR(mpfs_gpio->regs),
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"failed to initialise regmap\n");
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clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(clk))
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return dev_err_probe(dev, PTR_ERR(clk), "failed to get and enable clock\n");
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ngpios = MPFS_MAX_NUM_GPIO;
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device_property_read_u32(dev, "ngpios", &ngpios);
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if (ngpios > MPFS_MAX_NUM_GPIO)
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ngpios = MPFS_MAX_NUM_GPIO;
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mpfs_gpio->gc.direction_input = mpfs_gpio_direction_input;
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mpfs_gpio->gc.direction_output = mpfs_gpio_direction_output;
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mpfs_gpio->gc.get_direction = mpfs_gpio_get_direction;
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mpfs_gpio->gc.get = mpfs_gpio_get;
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mpfs_gpio->gc.set = mpfs_gpio_set;
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mpfs_gpio->gc.base = -1;
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mpfs_gpio->gc.ngpio = ngpios;
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mpfs_gpio->gc.label = dev_name(dev);
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mpfs_gpio->gc.parent = dev;
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mpfs_gpio->gc.owner = THIS_MODULE;
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return devm_gpiochip_add_data(dev, &mpfs_gpio->gc, mpfs_gpio);
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}
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static const struct of_device_id mpfs_gpio_of_ids[] = {
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{ .compatible = "microchip,mpfs-gpio", },
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{ /* end of list */ }
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};
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static struct platform_driver mpfs_gpio_driver = {
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.probe = mpfs_gpio_probe,
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.driver = {
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.name = "microchip,mpfs-gpio",
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.of_match_table = mpfs_gpio_of_ids,
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},
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};
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builtin_platform_driver(mpfs_gpio_driver);

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