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Lijo Lazaralexdeucher
Lijo Lazar
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alexdeucher
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Reapply: drm/amdgpu: Use generic hdp flush function
Except HDP v5.2 all use a common logic for HDP flush. Use a generic function. HDP v5.2 forces NO_KIQ logic, revisit it later. Reapply after fixing up an HDP regression. v2: merge the fix (Alex) Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
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6 files changed

+26
-68
lines changed

6 files changed

+26
-68
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
*/
2323
#include "amdgpu.h"
2424
#include "amdgpu_ras.h"
25+
#include <uapi/linux/kfd_ioctl.h>
2526

2627
int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
2728
{
@@ -46,3 +47,22 @@ int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
4647
/* hdp ras follows amdgpu_ras_block_late_init_default for late init */
4748
return 0;
4849
}
50+
51+
void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
52+
struct amdgpu_ring *ring)
53+
{
54+
if (!ring || !ring->funcs->emit_wreg) {
55+
WREG32((adev->rmmio_remap.reg_offset +
56+
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
57+
2,
58+
0);
59+
if (adev->nbio.funcs->get_memsize)
60+
adev->nbio.funcs->get_memsize(adev);
61+
} else {
62+
amdgpu_ring_emit_wreg(ring,
63+
(adev->rmmio_remap.reg_offset +
64+
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>
65+
2,
66+
0);
67+
}
68+
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,4 +44,6 @@ struct amdgpu_hdp {
4444
};
4545

4646
int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev);
47+
void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,
48+
struct amdgpu_ring *ring);
4749
#endif /* __AMDGPU_HDP_H__ */

‎drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c‎

Lines changed: 1 addition & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -36,22 +36,6 @@
3636
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
3737
#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
3838

39-
static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
40-
struct amdgpu_ring *ring)
41-
{
42-
if (!ring || !ring->funcs->emit_wreg) {
43-
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
44-
/* We just need to read back a register to post the write.
45-
* Reading back the remapped register causes problems on
46-
* some platforms so just read back the memory size register.
47-
*/
48-
if (adev->nbio.funcs->get_memsize)
49-
adev->nbio.funcs->get_memsize(adev);
50-
} else {
51-
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
52-
}
53-
}
54-
5539
static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
5640
struct amdgpu_ring *ring)
5741
{
@@ -185,7 +169,7 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = {
185169
};
186170

187171
const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
188-
.flush_hdp = hdp_v4_0_flush_hdp,
172+
.flush_hdp = amdgpu_hdp_generic_flush,
189173
.invalidate_hdp = hdp_v4_0_invalidate_hdp,
190174
.update_clock_gating = hdp_v4_0_update_clock_gating,
191175
.get_clock_gating_state = hdp_v4_0_get_clockgating_state,

‎drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c‎

Lines changed: 1 addition & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -27,22 +27,6 @@
2727
#include "hdp/hdp_5_0_0_sh_mask.h"
2828
#include <uapi/linux/kfd_ioctl.h>
2929

30-
static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
31-
struct amdgpu_ring *ring)
32-
{
33-
if (!ring || !ring->funcs->emit_wreg) {
34-
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
35-
/* We just need to read back a register to post the write.
36-
* Reading back the remapped register causes problems on
37-
* some platforms so just read back the memory size register.
38-
*/
39-
if (adev->nbio.funcs->get_memsize)
40-
adev->nbio.funcs->get_memsize(adev);
41-
} else {
42-
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
43-
}
44-
}
45-
4630
static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
4731
struct amdgpu_ring *ring)
4832
{
@@ -222,7 +206,7 @@ static void hdp_v5_0_init_registers(struct amdgpu_device *adev)
222206
}
223207

224208
const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {
225-
.flush_hdp = hdp_v5_0_flush_hdp,
209+
.flush_hdp = amdgpu_hdp_generic_flush,
226210
.invalidate_hdp = hdp_v5_0_invalidate_hdp,
227211
.update_clock_gating = hdp_v5_0_update_clock_gating,
228212
.get_clock_gating_state = hdp_v5_0_get_clockgating_state,

‎drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c‎

Lines changed: 1 addition & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -30,22 +30,6 @@
3030
#define regHDP_CLK_CNTL_V6_1 0xd5
3131
#define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
3232

33-
static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
34-
struct amdgpu_ring *ring)
35-
{
36-
if (!ring || !ring->funcs->emit_wreg) {
37-
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
38-
/* We just need to read back a register to post the write.
39-
* Reading back the remapped register causes problems on
40-
* some platforms so just read back the memory size register.
41-
*/
42-
if (adev->nbio.funcs->get_memsize)
43-
adev->nbio.funcs->get_memsize(adev);
44-
} else {
45-
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
46-
}
47-
}
48-
4933
static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
5034
bool enable)
5135
{
@@ -154,7 +138,7 @@ static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
154138
}
155139

156140
const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
157-
.flush_hdp = hdp_v6_0_flush_hdp,
141+
.flush_hdp = amdgpu_hdp_generic_flush,
158142
.update_clock_gating = hdp_v6_0_update_clock_gating,
159143
.get_clock_gating_state = hdp_v6_0_get_clockgating_state,
160144
};

‎drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c‎

Lines changed: 1 addition & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -27,22 +27,6 @@
2727
#include "hdp/hdp_7_0_0_sh_mask.h"
2828
#include <uapi/linux/kfd_ioctl.h>
2929

30-
static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
31-
struct amdgpu_ring *ring)
32-
{
33-
if (!ring || !ring->funcs->emit_wreg) {
34-
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
35-
/* We just need to read back a register to post the write.
36-
* Reading back the remapped register causes problems on
37-
* some platforms so just read back the memory size register.
38-
*/
39-
if (adev->nbio.funcs->get_memsize)
40-
adev->nbio.funcs->get_memsize(adev);
41-
} else {
42-
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
43-
}
44-
}
45-
4630
static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,
4731
bool enable)
4832
{
@@ -142,7 +126,7 @@ static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev,
142126
}
143127

144128
const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {
145-
.flush_hdp = hdp_v7_0_flush_hdp,
129+
.flush_hdp = amdgpu_hdp_generic_flush,
146130
.update_clock_gating = hdp_v7_0_update_clock_gating,
147131
.get_clock_gating_state = hdp_v7_0_get_clockgating_state,
148132
};

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