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anderssonandersson
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Merge branch '[email protected]' into clk-for-6.12
Merge the SM4450 display, camera and GPU bindings through a topic branch, to make it possible to merge them into the DeviceTree source branch as well.
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‎Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Camera Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <[email protected]>
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- Taniya Das <[email protected]>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and power
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domains on SM4450
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See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
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properties:
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compatible:
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const: qcom,sm4450-camcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Camera AHB clock source from GCC
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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clock-controller@ade0000 {
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compatible = "qcom,sm4450-camcc";
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reg = <0x0ade0000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_CAMERA_AHB_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <[email protected]>
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- Taniya Das <[email protected]>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM4450
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See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
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properties:
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compatible:
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const: qcom,sm4450-dispcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Display AHB clock source from GCC
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- description: sleep clock source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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clock-controller@af00000 {
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compatible = "qcom,sm4450-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&dsi0_phy_pll_out_byteclk>,
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<&dsi0_phy_pll_out_dsiclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml‎

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domains on Qualcomm SoCs.
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See also::
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include/dt-bindings/clock/qcom,sm4450-gpucc.h
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include/dt-bindings/clock/qcom,sm8450-gpucc.h
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include/dt-bindings/clock/qcom,sm8550-gpucc.h
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include/dt-bindings/reset/qcom,sm8450-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,sm4450-gpucc
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- qcom,sm8450-gpucc
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- qcom,sm8550-gpucc
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- qcom,sm8650-gpucc

‎include/dt-bindings/clock/qcom,sm4450-camcc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
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#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
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/* CAM_CC clocks */
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#define CAM_CC_BPS_AHB_CLK 0
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#define CAM_CC_BPS_AREG_CLK 1
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#define CAM_CC_BPS_CLK 2
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#define CAM_CC_BPS_CLK_SRC 3
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#define CAM_CC_CAMNOC_ATB_CLK 4
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#define CAM_CC_CAMNOC_AXI_CLK 5
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#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
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#define CAM_CC_CAMNOC_AXI_HF_CLK 7
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#define CAM_CC_CAMNOC_AXI_SF_CLK 8
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#define CAM_CC_CCI_0_CLK 9
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#define CAM_CC_CCI_0_CLK_SRC 10
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#define CAM_CC_CCI_1_CLK 11
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#define CAM_CC_CCI_1_CLK_SRC 12
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#define CAM_CC_CORE_AHB_CLK 13
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#define CAM_CC_CPAS_AHB_CLK 14
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#define CAM_CC_CPHY_RX_CLK_SRC 15
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#define CAM_CC_CRE_AHB_CLK 16
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#define CAM_CC_CRE_CLK 17
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#define CAM_CC_CRE_CLK_SRC 18
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#define CAM_CC_CSI0PHYTIMER_CLK 19
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20
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#define CAM_CC_CSI1PHYTIMER_CLK 21
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22
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#define CAM_CC_CSI2PHYTIMER_CLK 23
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24
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#define CAM_CC_CSIPHY0_CLK 25
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#define CAM_CC_CSIPHY1_CLK 26
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#define CAM_CC_CSIPHY2_CLK 27
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#define CAM_CC_FAST_AHB_CLK_SRC 28
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#define CAM_CC_ICP_ATB_CLK 29
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#define CAM_CC_ICP_CLK 30
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#define CAM_CC_ICP_CLK_SRC 31
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#define CAM_CC_ICP_CTI_CLK 32
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#define CAM_CC_ICP_TS_CLK 33
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#define CAM_CC_MCLK0_CLK 34
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#define CAM_CC_MCLK0_CLK_SRC 35
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#define CAM_CC_MCLK1_CLK 36
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#define CAM_CC_MCLK1_CLK_SRC 37
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#define CAM_CC_MCLK2_CLK 38
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#define CAM_CC_MCLK2_CLK_SRC 39
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#define CAM_CC_MCLK3_CLK 40
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#define CAM_CC_MCLK3_CLK_SRC 41
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#define CAM_CC_OPE_0_AHB_CLK 42
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#define CAM_CC_OPE_0_AREG_CLK 43
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#define CAM_CC_OPE_0_CLK 44
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#define CAM_CC_OPE_0_CLK_SRC 45
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#define CAM_CC_PLL0 46
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#define CAM_CC_PLL0_OUT_EVEN 47
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#define CAM_CC_PLL0_OUT_ODD 48
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#define CAM_CC_PLL1 49
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#define CAM_CC_PLL1_OUT_EVEN 50
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#define CAM_CC_PLL2 51
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#define CAM_CC_PLL2_OUT_EVEN 52
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#define CAM_CC_PLL3 53
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#define CAM_CC_PLL3_OUT_EVEN 54
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#define CAM_CC_PLL4 55
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#define CAM_CC_PLL4_OUT_EVEN 56
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#define CAM_CC_SLOW_AHB_CLK_SRC 57
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#define CAM_CC_SOC_AHB_CLK 58
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#define CAM_CC_SYS_TMR_CLK 59
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#define CAM_CC_TFE_0_AHB_CLK 60
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#define CAM_CC_TFE_0_CLK 61
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#define CAM_CC_TFE_0_CLK_SRC 62
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#define CAM_CC_TFE_0_CPHY_RX_CLK 63
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#define CAM_CC_TFE_0_CSID_CLK 64
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#define CAM_CC_TFE_0_CSID_CLK_SRC 65
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#define CAM_CC_TFE_1_AHB_CLK 66
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#define CAM_CC_TFE_1_CLK 67
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#define CAM_CC_TFE_1_CLK_SRC 68
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#define CAM_CC_TFE_1_CPHY_RX_CLK 69
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#define CAM_CC_TFE_1_CSID_CLK 70
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#define CAM_CC_TFE_1_CSID_CLK_SRC 71
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/* CAM_CC power domains */
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#define CAM_CC_CAMSS_TOP_GDSC 0
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/* CAM_CC resets */
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#define CAM_CC_BPS_BCR 0
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#define CAM_CC_CAMNOC_BCR 1
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#define CAM_CC_CAMSS_TOP_BCR 2
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#define CAM_CC_CCI_0_BCR 3
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#define CAM_CC_CCI_1_BCR 4
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#define CAM_CC_CPAS_BCR 5
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#define CAM_CC_CRE_BCR 6
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#define CAM_CC_CSI0PHY_BCR 7
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#define CAM_CC_CSI1PHY_BCR 8
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#define CAM_CC_CSI2PHY_BCR 9
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#define CAM_CC_ICP_BCR 10
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#define CAM_CC_MCLK0_BCR 11
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#define CAM_CC_MCLK1_BCR 12
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#define CAM_CC_MCLK2_BCR 13
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#define CAM_CC_MCLK3_BCR 14
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#define CAM_CC_OPE_0_BCR 15
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#define CAM_CC_TFE_0_BCR 16
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#define CAM_CC_TFE_1_BCR 17
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#endif

‎include/dt-bindings/clock/qcom,sm4450-dispcc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
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/* DISP_CC clocks */
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#define DISP_CC_MDSS_AHB1_CLK 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_ESC0_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK_SRC 8
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#define DISP_CC_MDSS_MDP1_CLK 9
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#define DISP_CC_MDSS_MDP_CLK 10
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#define DISP_CC_MDSS_MDP_CLK_SRC 11
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#define DISP_CC_MDSS_MDP_LUT1_CLK 12
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#define DISP_CC_MDSS_MDP_LUT_CLK 13
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14
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#define DISP_CC_MDSS_PCLK0_CLK 15
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
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#define DISP_CC_MDSS_ROT1_CLK 17
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#define DISP_CC_MDSS_ROT_CLK 18
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#define DISP_CC_MDSS_ROT_CLK_SRC 19
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#define DISP_CC_MDSS_RSCC_AHB_CLK 20
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21
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#define DISP_CC_MDSS_VSYNC1_CLK 22
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#define DISP_CC_MDSS_VSYNC_CLK 23
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
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#define DISP_CC_PLL0 25
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#define DISP_CC_PLL1 26
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#define DISP_CC_SLEEP_CLK 27
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#define DISP_CC_SLEEP_CLK_SRC 28
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#define DISP_CC_XO_CLK 29
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#define DISP_CC_XO_CLK_SRC 30
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#define DISP_CC_MDSS_CORE_INT2_GDSC 1
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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#endif

‎include/dt-bindings/clock/qcom,sm4450-gpucc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
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/* GPU_CC clocks */
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#define GPU_CC_AHB_CLK 0
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#define GPU_CC_CB_CLK 1
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#define GPU_CC_CRC_AHB_CLK 2
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#define GPU_CC_CX_FF_CLK 3
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#define GPU_CC_CX_GFX3D_CLK 4
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#define GPU_CC_CX_GFX3D_SLV_CLK 5
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#define GPU_CC_CX_GMU_CLK 6
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#define GPU_CC_CX_SNOC_DVM_CLK 7
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#define GPU_CC_CXO_AON_CLK 8
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#define GPU_CC_CXO_CLK 9
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#define GPU_CC_DEMET_CLK 10
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#define GPU_CC_DEMET_DIV_CLK_SRC 11
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#define GPU_CC_FF_CLK_SRC 12
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#define GPU_CC_FREQ_MEASURE_CLK 13
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#define GPU_CC_GMU_CLK_SRC 14
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#define GPU_CC_GX_CXO_CLK 15
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#define GPU_CC_GX_FF_CLK 16
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#define GPU_CC_GX_GFX3D_CLK 17
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#define GPU_CC_GX_GFX3D_CLK_SRC 18
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#define GPU_CC_GX_GFX3D_RDVM_CLK 19
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#define GPU_CC_GX_GMU_CLK 20
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#define GPU_CC_GX_VSENSE_CLK 21
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#define GPU_CC_HUB_AHB_DIV_CLK_SRC 22
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#define GPU_CC_HUB_AON_CLK 23
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#define GPU_CC_HUB_CLK_SRC 24
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#define GPU_CC_HUB_CX_INT_CLK 25
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#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 26
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#define GPU_CC_MEMNOC_GFX_CLK 27
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#define GPU_CC_MND1X_0_GFX3D_CLK 28
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#define GPU_CC_PLL0 29
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#define GPU_CC_PLL1 30
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#define GPU_CC_SLEEP_CLK 31
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#define GPU_CC_XO_CLK_SRC 32
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#define GPU_CC_XO_DIV_CLK_SRC 33
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/* GPU_CC power domains */
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#define GPU_CC_CX_GDSC 0
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#define GPU_CC_GX_GDSC 1
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/* GPU_CC resets */
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#define GPU_CC_ACD_BCR 0
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#define GPU_CC_CB_BCR 1
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#define GPU_CC_CX_BCR 2
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#define GPU_CC_FAST_HUB_BCR 3
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#define GPU_CC_FF_BCR 4
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#define GPU_CC_GFX3D_AON_BCR 5
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#define GPU_CC_GMU_BCR 6
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#define GPU_CC_GX_BCR 7
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#define GPU_CC_XO_BCR 8
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#define GPU_CC_GX_ACD_IROOT_BCR 9
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#define GPU_CC_RBCPR_BCR 10
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#endif

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