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Lijo Lazaralexdeucher
Lijo Lazar
authored and
alexdeucher
committed
drm/amdgpu: Use the right function for hdp flush
There are a few prechecks made before HDP flush like a flush is not required on APU bare metal. Using hdp callback directly bypasses those checks. Use amdgpu_device_flush_hdp which takes care of prechecks. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 1d9bff4)
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+23
-23
lines changed

10 files changed

+23
-23
lines changed

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6114,7 +6114,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
61146114
}
61156115

61166116
if (amdgpu_emu_mode == 1)
6117-
adev->hdp.funcs->flush_hdp(adev, NULL);
6117+
amdgpu_device_flush_hdp(adev, NULL);
61186118

61196119
tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
61206120
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -6192,7 +6192,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
61926192
}
61936193

61946194
if (amdgpu_emu_mode == 1)
6195-
adev->hdp.funcs->flush_hdp(adev, NULL);
6195+
amdgpu_device_flush_hdp(adev, NULL);
61966196

61976197
tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
61986198
tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
@@ -6269,7 +6269,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
62696269
}
62706270

62716271
if (amdgpu_emu_mode == 1)
6272-
adev->hdp.funcs->flush_hdp(adev, NULL);
6272+
amdgpu_device_flush_hdp(adev, NULL);
62736273

62746274
tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
62756275
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -6644,7 +6644,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
66446644
}
66456645

66466646
if (amdgpu_emu_mode == 1)
6647-
adev->hdp.funcs->flush_hdp(adev, NULL);
6647+
amdgpu_device_flush_hdp(adev, NULL);
66486648

66496649
tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
66506650
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2428,7 +2428,7 @@ static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
24282428
}
24292429

24302430
if (amdgpu_emu_mode == 1)
2431-
adev->hdp.funcs->flush_hdp(adev, NULL);
2431+
amdgpu_device_flush_hdp(adev, NULL);
24322432

24332433
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
24342434
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -2472,7 +2472,7 @@ static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
24722472
}
24732473

24742474
if (amdgpu_emu_mode == 1)
2475-
adev->hdp.funcs->flush_hdp(adev, NULL);
2475+
amdgpu_device_flush_hdp(adev, NULL);
24762476

24772477
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
24782478
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -2517,7 +2517,7 @@ static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
25172517
}
25182518

25192519
if (amdgpu_emu_mode == 1)
2520-
adev->hdp.funcs->flush_hdp(adev, NULL);
2520+
amdgpu_device_flush_hdp(adev, NULL);
25212521

25222522
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
25232523
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
@@ -3153,7 +3153,7 @@ static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
31533153
amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
31543154

31553155
if (amdgpu_emu_mode == 1)
3156-
adev->hdp.funcs->flush_hdp(adev, NULL);
3156+
amdgpu_device_flush_hdp(adev, NULL);
31573157

31583158
WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
31593159
lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
@@ -3371,7 +3371,7 @@ static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
33713371
amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
33723372

33733373
if (amdgpu_emu_mode == 1)
3374-
adev->hdp.funcs->flush_hdp(adev, NULL);
3374+
amdgpu_device_flush_hdp(adev, NULL);
33753375

33763376
WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
33773377
lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
@@ -4541,7 +4541,7 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
45414541
if (r)
45424542
return r;
45434543

4544-
adev->hdp.funcs->flush_hdp(adev, NULL);
4544+
amdgpu_device_flush_hdp(adev, NULL);
45454545

45464546
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
45474547
false : true;

‎drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2324,7 +2324,7 @@ static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
23242324
amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
23252325

23262326
if (amdgpu_emu_mode == 1)
2327-
adev->hdp.funcs->flush_hdp(adev, NULL);
2327+
amdgpu_device_flush_hdp(adev, NULL);
23282328

23292329
WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
23302330
lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
@@ -2468,7 +2468,7 @@ static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
24682468
amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
24692469

24702470
if (amdgpu_emu_mode == 1)
2471-
adev->hdp.funcs->flush_hdp(adev, NULL);
2471+
amdgpu_device_flush_hdp(adev, NULL);
24722472

24732473
WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
24742474
lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
@@ -3426,7 +3426,7 @@ static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
34263426
if (r)
34273427
return r;
34283428

3429-
adev->hdp.funcs->flush_hdp(adev, NULL);
3429+
amdgpu_device_flush_hdp(adev, NULL);
34303430

34313431
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
34323432
false : true;

‎drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
268268
ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
269269

270270
/* flush hdp cache */
271-
adev->hdp.funcs->flush_hdp(adev, NULL);
271+
amdgpu_device_flush_hdp(adev, NULL);
272272

273273
/* This is necessary for SRIOV as well as for GFXOFF to function
274274
* properly under bare metal
@@ -969,7 +969,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
969969
adev->hdp.funcs->init_registers(adev);
970970

971971
/* Flush HDP after it is initialized */
972-
adev->hdp.funcs->flush_hdp(adev, NULL);
972+
amdgpu_device_flush_hdp(adev, NULL);
973973

974974
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
975975
false : true;

‎drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
229229
ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
230230

231231
/* flush hdp cache */
232-
adev->hdp.funcs->flush_hdp(adev, NULL);
232+
amdgpu_device_flush_hdp(adev, NULL);
233233

234234
/* This is necessary for SRIOV as well as for GFXOFF to function
235235
* properly under bare metal
@@ -899,7 +899,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
899899
return r;
900900

901901
/* Flush HDP after it is initialized */
902-
adev->hdp.funcs->flush_hdp(adev, NULL);
902+
amdgpu_device_flush_hdp(adev, NULL);
903903

904904
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
905905
false : true;

‎drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
297297
return;
298298

299299
/* flush hdp cache */
300-
adev->hdp.funcs->flush_hdp(adev, NULL);
300+
amdgpu_device_flush_hdp(adev, NULL);
301301

302302
/* This is necessary for SRIOV as well as for GFXOFF to function
303303
* properly under bare metal
@@ -881,7 +881,7 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev)
881881
return r;
882882

883883
/* Flush HDP after it is initialized */
884-
adev->hdp.funcs->flush_hdp(adev, NULL);
884+
amdgpu_device_flush_hdp(adev, NULL);
885885

886886
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
887887
false : true;

‎drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2435,7 +2435,7 @@ static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block)
24352435
adev->hdp.funcs->init_registers(adev);
24362436

24372437
/* After HDP is initialized, flush HDP.*/
2438-
adev->hdp.funcs->flush_hdp(adev, NULL);
2438+
amdgpu_device_flush_hdp(adev, NULL);
24392439

24402440
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
24412441
value = false;

‎drivers/gpu/drm/amd/amdgpu/psp_v11_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -533,7 +533,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
533533
}
534534

535535
memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
536-
adev->hdp.funcs->flush_hdp(adev, NULL);
536+
amdgpu_device_flush_hdp(adev, NULL);
537537
vfree(buf);
538538
drm_dev_exit(idx);
539539
} else {

‎drivers/gpu/drm/amd/amdgpu/psp_v13_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -610,7 +610,7 @@ static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
610610
}
611611

612612
memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
613-
adev->hdp.funcs->flush_hdp(adev, NULL);
613+
amdgpu_device_flush_hdp(adev, NULL);
614614
vfree(buf);
615615
drm_dev_exit(idx);
616616
} else {

‎drivers/gpu/drm/amd/amdgpu/psp_v14_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -498,7 +498,7 @@ static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)
498498
}
499499

500500
memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
501-
adev->hdp.funcs->flush_hdp(adev, NULL);
501+
amdgpu_device_flush_hdp(adev, NULL);
502502
vfree(buf);
503503
drm_dev_exit(idx);
504504
} else {

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