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Merge tag 'drm-msm-next-2025-03-09' of https://gitlab.freedesktop.org/drm/msm into drm-next
Updates for v6.15 GPU: - Fix obscure GMU suspend failure - Expose syncobj timeline support - Extend GPU devcoredump with pagetable info - a623 support - Fix a6xx gen1/gen2 indexed-register blocks in gpu snapshot / devcoredump Display: - Add cpu-cfg interconnect paths on SM8560 and SM8650 - Introduce KMS OMMU fault handler, causing devcoredump snapshot - Fixed error pointer dereference in msm_kms_init_aspace() DPU: - Fix mode_changing handling - Add writeback support on SM6150 (QCS615) - Fix DSC programming in 1:1:1 topology - Reworked hardware resource allocation, moving it to the CRTC code - Enabled support for Concurrent WriteBack (CWB) on SM8650 - Enabled CDM blocks on all relevant platforms - Reworked debugfs interface for BW/clocks debugging - Clear perf params before calculating bw - Support YUV formats on writeback - Fixed double inclusion - Fixed writeback in YUV formats when using cloned output, Dropped wb2_formats_rgb - Corrected dpu_crtc_check_mode_changed and struct dpu_encoder_virt kerneldocs - Fixed uninitialized variable in dpu_crtc_kickoff_clone_mode() DSI: - DSC-related fixes - Rework clock programming DSI PHY: - Fix 7nm (and lower) PHY programming - Add proper DT schema definitions for DSI PHY clocks HDMI: - Rework the driver, enabling the use of the HDMI Connector framework Bindings: - Added eDP PHY on SA8775P Misc: - mailmap/MAINTAINERS: update Dmitry's email addr Signed-off-by: Dave Airlie <[email protected]> From: Rob Clark <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGu-rbEFzQQ-me6qRLgBOJ=Xro1PL=PhtKJ-K9=bCaiK0w@mail.gmail.com
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‎.mailmap‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -200,10 +200,11 @@ Dengcheng Zhu <[email protected]> <[email protected]>
200200
Dengcheng Zhu <[email protected]> <[email protected]>
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<[email protected]> <[email protected]>
202202
Dikshita Agarwal <[email protected]> <[email protected]>
203-
Dmitry Baryshkov <[email protected]>
204-
Dmitry Baryshkov <[email protected]> <[[email protected]]>
205-
Dmitry Baryshkov <[email protected]> <[email protected]>
206-
Dmitry Baryshkov <[email protected]> <[email protected]>
203+
Dmitry Baryshkov <[email protected]> <[email protected]>
204+
Dmitry Baryshkov <[email protected]> <[[email protected]]>
205+
Dmitry Baryshkov <[email protected]> <[email protected]>
206+
Dmitry Baryshkov <[email protected]> <[email protected]>
207+
Dmitry Baryshkov <[email protected]> <[email protected]>
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Dmitry Safonov <[email protected]> <[email protected]>
208209
Dmitry Safonov <[email protected]> <[email protected]>
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Dmitry Safonov <[email protected]> <[email protected]>

‎Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml‎

Lines changed: 11 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -231,6 +231,7 @@ allOf:
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then:
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properties:
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clocks:
234+
minItems: 7
234235
maxItems: 7
235236
clock-names:
236237
items:
@@ -248,29 +249,12 @@ allOf:
248249
contains:
249250
enum:
250251
- qcom,msm8916-dsi-ctrl
251-
then:
252-
properties:
253-
clocks:
254-
maxItems: 6
255-
clock-names:
256-
items:
257-
- const: mdp_core
258-
- const: iface
259-
- const: bus
260-
- const: byte
261-
- const: pixel
262-
- const: core
263-
264-
- if:
265-
properties:
266-
compatible:
267-
contains:
268-
enum:
269252
- qcom,msm8953-dsi-ctrl
270253
- qcom,msm8976-dsi-ctrl
271254
then:
272255
properties:
273256
clocks:
257+
minItems: 6
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maxItems: 6
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clock-names:
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items:
@@ -291,6 +275,7 @@ allOf:
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then:
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properties:
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clocks:
278+
minItems: 7
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maxItems: 7
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clock-names:
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items:
@@ -311,6 +296,7 @@ allOf:
311296
then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
@@ -328,28 +314,13 @@ allOf:
328314
contains:
329315
enum:
330316
- qcom,msm8998-dsi-ctrl
331-
- qcom,sm6125-dsi-ctrl
332-
- qcom,sm6350-dsi-ctrl
333-
then:
334-
properties:
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clocks:
336-
maxItems: 6
337-
clock-names:
338-
items:
339-
- const: byte
340-
- const: byte_intf
341-
- const: pixel
342-
- const: core
343-
- const: iface
344-
- const: bus
345-
346-
- if:
347-
properties:
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compatible:
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contains:
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enum:
351317
- qcom,sc7180-dsi-ctrl
352318
- qcom,sc7280-dsi-ctrl
319+
- qcom,sdm845-dsi-ctrl
320+
- qcom,sm6115-dsi-ctrl
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- qcom,sm6125-dsi-ctrl
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- qcom,sm6350-dsi-ctrl
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- qcom,sm6375-dsi-ctrl
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- qcom,sm6150-dsi-ctrl
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- qcom,sm7150-dsi-ctrl
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- qcom,sm8150-dsi-ctrl
@@ -361,6 +332,7 @@ allOf:
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then:
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properties:
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clocks:
335+
minItems: 6
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maxItems: 6
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clock-names:
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items:
@@ -380,6 +352,7 @@ allOf:
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then:
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properties:
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clocks:
355+
minItems: 9
383356
maxItems: 9
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clock-names:
385358
items:
@@ -393,27 +366,6 @@ allOf:
393366
- const: pixel
394367
- const: core
395368

396-
- if:
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properties:
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compatible:
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contains:
400-
enum:
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- qcom,sdm845-dsi-ctrl
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- qcom,sm6115-dsi-ctrl
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- qcom,sm6375-dsi-ctrl
404-
then:
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properties:
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clocks:
407-
maxItems: 6
408-
clock-names:
409-
items:
410-
- const: byte
411-
- const: byte_intf
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- const: pixel
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- const: core
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- const: iface
415-
- const: bus
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unevaluatedProperties: false
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419371
examples:

‎Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml‎

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@@ -15,6 +15,8 @@ description:
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properties:
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"#clock-cells":
1717
const: 1
18+
description:
19+
See include/dt-bindings/clock/qcom,dsi-phy-28nm.h for clock IDs.
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1921
"#phy-cells":
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const: 0

‎Documentation/devicetree/bindings/display/msm/gmu.yaml‎

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@@ -123,6 +123,7 @@ allOf:
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compatible:
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contains:
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enum:
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- qcom,adreno-gmu-623.0
126127
- qcom,adreno-gmu-635.0
127128
- qcom,adreno-gmu-660.1
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- qcom,adreno-gmu-663.0

‎Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml‎

Lines changed: 30 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,13 @@ patternProperties:
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items:
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- const: qcom,sa8775p-dp
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55+
"^phy@[0-9a-f]+$":
56+
type: object
57+
additionalProperties: true
58+
properties:
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compatible:
60+
const: qcom,sa8775p-edp-phy
61+
5562
required:
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- compatible
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@@ -61,6 +68,7 @@ examples:
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- |
6269
#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
71+
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
6472
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -158,6 +166,26 @@ examples:
158166
};
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};
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169+
mdss0_dp0_phy: phy@aec2a00 {
170+
compatible = "qcom,sa8775p-edp-phy";
171+
172+
reg = <0x0aec2a00 0x200>,
173+
<0x0aec2200 0xd0>,
174+
<0x0aec2600 0xd0>,
175+
<0x0aec2000 0x1c8>;
176+
177+
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
178+
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
179+
clock-names = "aux",
180+
"cfg_ahb";
181+
182+
#clock-cells = <1>;
183+
#phy-cells = <0>;
184+
185+
vdda-phy-supply = <&vreg_l1c>;
186+
vdda-pll-supply = <&vreg_l4a>;
187+
};
188+
161189
displayport-controller@af54000 {
162190
compatible = "qcom,sa8775p-dp";
163191
@@ -186,9 +214,9 @@ examples:
186214
187215
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
188216
<&dispcc_mdss_dptx0_pixel0_clk_src>;
189-
assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;
217+
assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
190218
191-
phys = <&mdss0_edp_phy>;
219+
phys = <&mdss0_dp0_phy>;
192220
phy-names = "dp";
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194222
operating-points-v2 = <&dp_opp_table>;

‎Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -30,10 +30,14 @@ properties:
3030
maxItems: 1
3131

3232
interconnects:
33-
maxItems: 2
33+
items:
34+
- description: Interconnect path from mdp0 port to the data bus
35+
- description: Interconnect path from CPU to the reg bus
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3537
interconnect-names:
36-
maxItems: 2
38+
items:
39+
- const: mdp0-mem
40+
- const: cpu-cfg
3741

3842
patternProperties:
3943
"^display-controller@[0-9a-f]+$":
@@ -91,9 +95,9 @@ examples:
9195
reg = <0x0ae00000 0x1000>;
9296
reg-names = "mdss";
9397
94-
interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
95-
<&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
96-
interconnect-names = "mdp0-mem", "mdp1-mem";
98+
interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
99+
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
100+
interconnect-names = "mdp0-mem", "cpu-cfg";
97101
98102
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
99103

‎Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,10 +29,14 @@ properties:
2929
maxItems: 1
3030

3131
interconnects:
32-
maxItems: 2
32+
items:
33+
- description: Interconnect path from mdp0 port to the data bus
34+
- description: Interconnect path from CPU to the reg bus
3335

3436
interconnect-names:
35-
maxItems: 2
37+
items:
38+
- const: mdp0-mem
39+
- const: cpu-cfg
3640

3741
patternProperties:
3842
"^display-controller@[0-9a-f]+$":
@@ -75,12 +79,17 @@ examples:
7579
#include <dt-bindings/clock/qcom,rpmh.h>
7680
#include <dt-bindings/interrupt-controller/arm-gic.h>
7781
#include <dt-bindings/power/qcom,rpmhpd.h>
82+
#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
7883
7984
display-subsystem@ae00000 {
8085
compatible = "qcom,sm8650-mdss";
8186
reg = <0x0ae00000 0x1000>;
8287
reg-names = "mdss";
8388
89+
interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
90+
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
91+
interconnect-names = "mdp0-mem", "cpu-cfg";
92+
8493
resets = <&dispcc_core_bcr>;
8594
8695
power-domains = <&dispcc_gdsc>;

‎MAINTAINERS‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7389,7 +7389,7 @@ F: include/uapi/drm/msm_drm.h
73897389
DRM DRIVER for Qualcomm display hardware
73907390
M: Rob Clark <[email protected]>
73917391
M: Abhinav Kumar <[email protected]>
7392-
M: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
7392+
M: Dmitry Baryshkov <lumag@kernel.org>
73937393
R: Sean Paul <[email protected]>
73947394
R: Marijn Suijten <[email protected]>
73957395
L: [email protected]
@@ -7401,6 +7401,7 @@ T: git https://gitlab.freedesktop.org/drm/msm.git
74017401
F: Documentation/devicetree/bindings/display/msm/
74027402
F: drivers/gpu/drm/ci/xfails/msm*
74037403
F: drivers/gpu/drm/msm/
7404+
F: include/dt-bindings/clock/qcom,dsi-phy-28nm.h
74047405
F: include/uapi/drm/msm_drm.h
74057406

74067407
DRM DRIVER FOR NOVATEK NT35510 PANELS

‎drivers/gpu/drm/msm/Kconfig‎

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@@ -170,6 +170,8 @@ config DRM_MSM_HDMI
170170
bool "Enable HDMI support in MSM DRM driver"
171171
depends on DRM_MSM
172172
default y
173+
select DRM_DISPLAY_HDMI_HELPER
174+
select DRM_DISPLAY_HDMI_STATE_HELPER
173175
help
174176
Compile in support for the HDMI output MSM DRM driver. It can
175177
be a primary or a secondary display on device. Note that this is used

‎drivers/gpu/drm/msm/adreno/a6xx_catalog.c‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = {
879879
{ 0, 0 },
880880
{ 137, 1 },
881881
),
882+
}, {
883+
.chip_ids = ADRENO_CHIP_IDS(0x06020300),
884+
.family = ADRENO_6XX_GEN3,
885+
.fw = {
886+
[ADRENO_FW_SQE] = "a650_sqe.fw",
887+
[ADRENO_FW_GMU] = "a623_gmu.bin",
888+
},
889+
.gmem = SZ_512K,
890+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
891+
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
892+
ADRENO_QUIRK_HAS_HW_APRIV,
893+
.init = a6xx_gpu_init,
894+
.a6xx = &(const struct a6xx_info) {
895+
.hwcg = a690_hwcg,
896+
.protect = &a650_protect,
897+
.gmu_cgc_mode = 0x00020200,
898+
.prim_fifo_threshold = 0x00010000,
899+
.bcms = (const struct a6xx_bcm[]) {
900+
{ .name = "SH0", .buswidth = 16 },
901+
{ .name = "MC0", .buswidth = 4 },
902+
{
903+
.name = "ACV",
904+
.fixed = true,
905+
.perfmode = BIT(3),
906+
},
907+
{ /* sentinel */ },
908+
},
909+
},
910+
.address_space_size = SZ_16G,
882911
}, {
883912
.chip_ids = ADRENO_CHIP_IDS(
884913
0x06030001,

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