Commit cad4dda
serial: 8250_dw: Add Sophgo SG2044 quirk
SG2044 relys on an internal divisor when calculating bitrate, which
means a wrong clock for the most common bitrates. So add a quirk for
this uart device to skip the set rate call and only relys on the
internal UART divisor.
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Ilpo Järvinen <[email protected]>
Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>1 parent a54108c commit cad4dda
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