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Merge tag 'iommu-updates-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel: "Core changes: - iova_magazine_alloc() optimization - Make flush-queue an IOMMU driver capability - Consolidate the error handling around device attachment AMD IOMMU changes: - AVIC Interrupt Remapping Improvements - Some minor fixes and cleanups Intel VT-d changes from Lu Baolu: - Small and misc cleanups ARM-SMMU changes from Will Deacon: - Device-tree binding updates: - Add missing clocks for SC8280XP and SA8775 Adreno SMMUs - Add two new Qualcomm SMMUs in SDX75 and SM6375 - Workarounds for Arm MMU-700 errata: - 1076982: Avoid use of SEV-based cmdq wakeup - 2812531: Terminate command batches with a CMD_SYNC - Enforce single-stage translation to avoid nesting-related errata - Set the correct level hint for range TLB invalidation on teardown .. and some other minor fixes and cleanups (including Freescale PAMU and virtio-iommu changes)" * tag 'iommu-updates-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (50 commits) iommu/vt-d: Remove commented-out code iommu/vt-d: Remove two WARN_ON in domain_context_mapping_one() iommu/vt-d: Handle the failure case of dmar_reenable_qi() iommu/vt-d: Remove unnecessary (void*) conversions iommu/amd: Remove extern from function prototypes iommu/amd: Use BIT/BIT_ULL macro to define bit fields iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro iommu/amd: Fix compile error for unused function iommu/amd: Improving Interrupt Remapping Table Invalidation iommu/amd: Do not Invalidate IRT when IRTE caching is disabled iommu/amd: Introduce Disable IRTE Caching Support iommu/amd: Remove the unused struct amd_ir_data.ref iommu/amd: Switch amd_iommu_update_ga() to use modify_irte_ga() iommu/arm-smmu-v3: Set TTL invalidation hint better iommu/arm-smmu-v3: Document nesting-related errata iommu/arm-smmu-v3: Add explicit feature for nesting iommu/arm-smmu-v3: Document MMU-700 erratum 2812531 iommu/arm-smmu-v3: Work around MMU-600 erratum 1076982 dt-bindings: arm-smmu: Add SDX75 SMMU compatible dt-bindings: arm-smmu: Add SM6375 GPU SMMU ...
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‎.clang-format‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -254,6 +254,7 @@ ForEachMacros:
254254
- 'for_each_free_mem_range'
255255
- 'for_each_free_mem_range_reverse'
256256
- 'for_each_func_rsrc'
257+
- 'for_each_group_device'
257258
- 'for_each_group_evsel'
258259
- 'for_each_group_member'
259260
- 'for_each_hstate'

‎Documentation/admin-guide/kernel-parameters.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -323,6 +323,7 @@
323323
option with care.
324324
pgtbl_v1 - Use v1 page table for DMA-API (Default).
325325
pgtbl_v2 - Use v2 page table for DMA-API.
326+
irtcachedis - Disable Interrupt Remapping Table (IRT) caching.
326327

327328
amd_iommu_dump= [HW,X86-64]
328329
Enable AMD IOMMU driver option to dump the ACPI table

‎Documentation/arch/arm64/silicon-errata.rst‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,10 @@ stable kernels.
140140
+----------------+-----------------+-----------------+-----------------------------+
141141
| ARM | MMU-500 | #841119,826419 | N/A |
142142
+----------------+-----------------+-----------------+-----------------------------+
143+
| ARM | MMU-600 | #1076982,1209401| N/A |
144+
+----------------+-----------------+-----------------+-----------------------------+
145+
| ARM | MMU-700 | #2268618,2812531| N/A |
146+
+----------------+-----------------+-----------------+-----------------------------+
143147
+----------------+-----------------+-----------------+-----------------------------+
144148
| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 |
145149
+----------------+-----------------+-----------------+-----------------------------+

‎Documentation/devicetree/bindings/iommu/arm,smmu.yaml‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ properties:
2929
- qcom,msm8996-smmu-v2
3030
- qcom,msm8998-smmu-v2
3131
- qcom,sdm630-smmu-v2
32+
- qcom,sm6375-smmu-v2
3233
- const: qcom,smmu-v2
3334

3435
- description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
@@ -45,6 +46,7 @@ properties:
4546
- qcom,sdm845-smmu-500
4647
- qcom,sdx55-smmu-500
4748
- qcom,sdx65-smmu-500
49+
- qcom,sdx75-smmu-500
4850
- qcom,sm6115-smmu-500
4951
- qcom,sm6125-smmu-500
5052
- qcom,sm6350-smmu-500
@@ -79,7 +81,9 @@ properties:
7981
- description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
8082
items:
8183
- enum:
84+
- qcom,sa8775p-smmu-500
8285
- qcom,sc7280-smmu-500
86+
- qcom,sc8280xp-smmu-500
8387
- qcom,sm6115-smmu-500
8488
- qcom,sm6125-smmu-500
8589
- qcom,sm8150-smmu-500
@@ -267,6 +271,7 @@ allOf:
267271
enum:
268272
- qcom,msm8998-smmu-v2
269273
- qcom,sdm630-smmu-v2
274+
- qcom,sm6375-smmu-v2
270275
then:
271276
anyOf:
272277
- properties:
@@ -331,7 +336,10 @@ allOf:
331336
properties:
332337
compatible:
333338
contains:
334-
const: qcom,sc7280-smmu-500
339+
enum:
340+
- qcom,sa8775p-smmu-500
341+
- qcom,sc7280-smmu-500
342+
- qcom,sc8280xp-smmu-500
335343
then:
336344
properties:
337345
clock-names:
@@ -413,10 +421,8 @@ allOf:
413421
- nvidia,smmu-500
414422
- qcom,qcm2290-smmu-500
415423
- qcom,qdu1000-smmu-500
416-
- qcom,sa8775p-smmu-500
417424
- qcom,sc7180-smmu-500
418425
- qcom,sc8180x-smmu-500
419-
- qcom,sc8280xp-smmu-500
420426
- qcom,sdm670-smmu-500
421427
- qcom,sdm845-smmu-500
422428
- qcom,sdx55-smmu-500

‎arch/powerpc/sysdev/fsl_pci.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1353,6 +1353,7 @@ static struct platform_driver fsl_pci_driver = {
13531353
.of_match_table = pci_ids,
13541354
},
13551355
.probe = fsl_pci_probe,
1356+
.driver_managed_dma = true,
13561357
};
13571358

13581359
static int __init fsl_pci_init(void)

‎drivers/iommu/amd/amd_iommu.h‎

Lines changed: 46 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -11,12 +11,15 @@
1111

1212
#include "amd_iommu_types.h"
1313

14-
extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
15-
extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
16-
extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
17-
extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
18-
extern void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
19-
extern void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
14+
irqreturn_t amd_iommu_int_thread(int irq, void *data);
15+
irqreturn_t amd_iommu_int_handler(int irq, void *data);
16+
void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
17+
void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
18+
void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
19+
int amd_iommu_init_devices(void);
20+
void amd_iommu_uninit_devices(void);
21+
void amd_iommu_init_notifier(void);
22+
void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
2023

2124
#ifdef CONFIG_AMD_IOMMU_DEBUGFS
2225
void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
@@ -25,45 +28,44 @@ static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
2528
#endif
2629

2730
/* Needed for interrupt remapping */
28-
extern int amd_iommu_prepare(void);
29-
extern int amd_iommu_enable(void);
30-
extern void amd_iommu_disable(void);
31-
extern int amd_iommu_reenable(int);
32-
extern int amd_iommu_enable_faulting(void);
31+
int amd_iommu_prepare(void);
32+
int amd_iommu_enable(void);
33+
void amd_iommu_disable(void);
34+
int amd_iommu_reenable(int mode);
35+
int amd_iommu_enable_faulting(void);
3336
extern int amd_iommu_guest_ir;
3437
extern enum io_pgtable_fmt amd_iommu_pgtable;
3538
extern int amd_iommu_gpt_level;
3639

3740
/* IOMMUv2 specific functions */
3841
struct iommu_domain;
3942

40-
extern bool amd_iommu_v2_supported(void);
41-
extern struct amd_iommu *get_amd_iommu(unsigned int idx);
42-
extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
43-
extern bool amd_iommu_pc_supported(void);
44-
extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
45-
extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
46-
u8 fxn, u64 *value);
47-
extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
48-
u8 fxn, u64 *value);
49-
50-
extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
51-
extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
52-
extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
53-
extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
54-
extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
55-
u64 address);
56-
extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
57-
extern void amd_iommu_domain_update(struct protection_domain *domain);
58-
extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
59-
extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
60-
extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
61-
extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
62-
unsigned long cr3);
63-
extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
43+
bool amd_iommu_v2_supported(void);
44+
struct amd_iommu *get_amd_iommu(unsigned int idx);
45+
u8 amd_iommu_pc_get_max_banks(unsigned int idx);
46+
bool amd_iommu_pc_supported(void);
47+
u8 amd_iommu_pc_get_max_counters(unsigned int idx);
48+
int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
49+
u8 fxn, u64 *value);
50+
int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
51+
u8 fxn, u64 *value);
52+
53+
int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
54+
int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
55+
void amd_iommu_domain_direct_map(struct iommu_domain *dom);
56+
int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
57+
int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address);
58+
void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
59+
void amd_iommu_domain_update(struct protection_domain *domain);
60+
void amd_iommu_domain_flush_complete(struct protection_domain *domain);
61+
void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
62+
int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
63+
int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
64+
unsigned long cr3);
65+
int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
6466

6567
#ifdef CONFIG_IRQ_REMAP
66-
extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
68+
int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
6769
#else
6870
static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
6971
{
@@ -75,8 +77,8 @@ static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
7577
#define PPR_INVALID 0x1
7678
#define PPR_FAILURE 0xf
7779

78-
extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
79-
int status, int tag);
80+
int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
81+
int status, int tag);
8082

8183
static inline bool is_rd890_iommu(struct pci_dev *pdev)
8284
{
@@ -129,20 +131,19 @@ static inline void *alloc_pgtable_page(int nid, gfp_t gfp)
129131
return page ? page_address(page) : NULL;
130132
}
131133

132-
extern bool translation_pre_enabled(struct amd_iommu *iommu);
133-
extern bool amd_iommu_is_attach_deferred(struct device *dev);
134-
extern int __init add_special_device(u8 type, u8 id, u32 *devid,
135-
bool cmd_line);
134+
bool translation_pre_enabled(struct amd_iommu *iommu);
135+
bool amd_iommu_is_attach_deferred(struct device *dev);
136+
int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
136137

137138
#ifdef CONFIG_DMI
138139
void amd_iommu_apply_ivrs_quirks(void);
139140
#else
140141
static inline void amd_iommu_apply_ivrs_quirks(void) { }
141142
#endif
142143

143-
extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
144-
u64 *root, int mode);
145-
extern struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
144+
void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
145+
u64 *root, int mode);
146+
struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
146147

147148
extern u64 amd_iommu_efr;
148149
extern u64 amd_iommu_efr2;

‎drivers/iommu/amd/amd_iommu_types.h‎

Lines changed: 45 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -84,21 +84,21 @@
8484

8585

8686
/* Extended Feature Bits */
87-
#define FEATURE_PREFETCH (1ULL<<0)
88-
#define FEATURE_PPR (1ULL<<1)
89-
#define FEATURE_X2APIC (1ULL<<2)
90-
#define FEATURE_NX (1ULL<<3)
91-
#define FEATURE_GT (1ULL<<4)
92-
#define FEATURE_IA (1ULL<<6)
93-
#define FEATURE_GA (1ULL<<7)
94-
#define FEATURE_HE (1ULL<<8)
95-
#define FEATURE_PC (1ULL<<9)
87+
#define FEATURE_PREFETCH BIT_ULL(0)
88+
#define FEATURE_PPR BIT_ULL(1)
89+
#define FEATURE_X2APIC BIT_ULL(2)
90+
#define FEATURE_NX BIT_ULL(3)
91+
#define FEATURE_GT BIT_ULL(4)
92+
#define FEATURE_IA BIT_ULL(6)
93+
#define FEATURE_GA BIT_ULL(7)
94+
#define FEATURE_HE BIT_ULL(8)
95+
#define FEATURE_PC BIT_ULL(9)
9696
#define FEATURE_GATS_SHIFT (12)
9797
#define FEATURE_GATS_MASK (3ULL)
98-
#define FEATURE_GAM_VAPIC (1ULL<<21)
99-
#define FEATURE_GIOSUP (1ULL<<48)
100-
#define FEATURE_EPHSUP (1ULL<<50)
101-
#define FEATURE_SNP (1ULL<<63)
98+
#define FEATURE_GAM_VAPIC BIT_ULL(21)
99+
#define FEATURE_GIOSUP BIT_ULL(48)
100+
#define FEATURE_EPHSUP BIT_ULL(50)
101+
#define FEATURE_SNP BIT_ULL(63)
102102

103103
#define FEATURE_PASID_SHIFT 32
104104
#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
@@ -120,13 +120,13 @@
120120
#define PASID_MASK 0x0000ffff
121121

122122
/* MMIO status bits */
123-
#define MMIO_STATUS_EVT_OVERFLOW_INT_MASK (1 << 0)
124-
#define MMIO_STATUS_EVT_INT_MASK (1 << 1)
125-
#define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
126-
#define MMIO_STATUS_PPR_INT_MASK (1 << 6)
127-
#define MMIO_STATUS_GALOG_RUN_MASK (1 << 8)
128-
#define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
129-
#define MMIO_STATUS_GALOG_INT_MASK (1 << 10)
123+
#define MMIO_STATUS_EVT_OVERFLOW_INT_MASK BIT(0)
124+
#define MMIO_STATUS_EVT_INT_MASK BIT(1)
125+
#define MMIO_STATUS_COM_WAIT_INT_MASK BIT(2)
126+
#define MMIO_STATUS_PPR_INT_MASK BIT(6)
127+
#define MMIO_STATUS_GALOG_RUN_MASK BIT(8)
128+
#define MMIO_STATUS_GALOG_OVERFLOW_MASK BIT(9)
129+
#define MMIO_STATUS_GALOG_INT_MASK BIT(10)
130130

131131
/* event logging constants */
132132
#define EVENT_ENTRY_SIZE 0x10
@@ -174,6 +174,7 @@
174174
#define CONTROL_GAINT_EN 29
175175
#define CONTROL_XT_EN 50
176176
#define CONTROL_INTCAPXT_EN 51
177+
#define CONTROL_IRTCACHEDIS 59
177178
#define CONTROL_SNPAVIC_EN 61
178179

179180
#define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
@@ -283,7 +284,7 @@
283284
#define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
284285

285286
/* Bit value definition for dte irq remapping fields*/
286-
#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
287+
#define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6)
287288
#define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
288289
#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
289290
#define DTE_IRQ_REMAP_ENABLE 1ULL
@@ -369,23 +370,23 @@
369370
/*
370371
* Bit value definition for I/O PTE fields
371372
*/
372-
#define IOMMU_PTE_PR (1ULL << 0)
373-
#define IOMMU_PTE_U (1ULL << 59)
374-
#define IOMMU_PTE_FC (1ULL << 60)
375-
#define IOMMU_PTE_IR (1ULL << 61)
376-
#define IOMMU_PTE_IW (1ULL << 62)
373+
#define IOMMU_PTE_PR BIT_ULL(0)
374+
#define IOMMU_PTE_U BIT_ULL(59)
375+
#define IOMMU_PTE_FC BIT_ULL(60)
376+
#define IOMMU_PTE_IR BIT_ULL(61)
377+
#define IOMMU_PTE_IW BIT_ULL(62)
377378

378379
/*
379380
* Bit value definition for DTE fields
380381
*/
381-
#define DTE_FLAG_V (1ULL << 0)
382-
#define DTE_FLAG_TV (1ULL << 1)
383-
#define DTE_FLAG_IR (1ULL << 61)
384-
#define DTE_FLAG_IW (1ULL << 62)
385-
386-
#define DTE_FLAG_IOTLB (1ULL << 32)
387-
#define DTE_FLAG_GIOV (1ULL << 54)
388-
#define DTE_FLAG_GV (1ULL << 55)
382+
#define DTE_FLAG_V BIT_ULL(0)
383+
#define DTE_FLAG_TV BIT_ULL(1)
384+
#define DTE_FLAG_IR BIT_ULL(61)
385+
#define DTE_FLAG_IW BIT_ULL(62)
386+
387+
#define DTE_FLAG_IOTLB BIT_ULL(32)
388+
#define DTE_FLAG_GIOV BIT_ULL(54)
389+
#define DTE_FLAG_GV BIT_ULL(55)
389390
#define DTE_FLAG_MASK (0x3ffULL << 32)
390391
#define DTE_GLX_SHIFT (56)
391392
#define DTE_GLX_MASK (3)
@@ -439,13 +440,13 @@
439440
#define MAX_DOMAIN_ID 65536
440441

441442
/* Protection domain flags */
442-
#define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
443-
#define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
443+
#define PD_DMA_OPS_MASK BIT(0) /* domain used for dma_ops */
444+
#define PD_DEFAULT_MASK BIT(1) /* domain is a default dma_ops
444445
domain for an IOMMU */
445-
#define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
446+
#define PD_PASSTHROUGH_MASK BIT(2) /* domain has no page
446447
translation */
447-
#define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */
448-
#define PD_GIOV_MASK (1UL << 4) /* domain enable GIOV support */
448+
#define PD_IOMMUV2_MASK BIT(3) /* domain has gcr3 table */
449+
#define PD_GIOV_MASK BIT(4) /* domain enable GIOV support */
449450

450451
extern bool amd_iommu_dump;
451452
#define DUMP_printk(format, arg...) \
@@ -716,6 +717,9 @@ struct amd_iommu {
716717
/* if one, we need to send a completion wait command */
717718
bool need_sync;
718719

720+
/* true if disable irte caching */
721+
bool irtcachedis_enabled;
722+
719723
/* Handle for IOMMU core code */
720724
struct iommu_device iommu;
721725

@@ -748,7 +752,7 @@ struct amd_iommu {
748752

749753
u32 flags;
750754
volatile u64 *cmd_sem;
751-
u64 cmd_sem_val;
755+
atomic64_t cmd_sem_val;
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#ifdef CONFIG_AMD_IOMMU_DEBUGFS
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/* DebugFS Info */
@@ -882,7 +886,7 @@ extern int amd_iommu_max_glx_val;
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* This function flushes all internal caches of
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* the IOMMU used by this driver.
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*/
885-
extern void iommu_flush_all_caches(struct amd_iommu *iommu);
889+
void iommu_flush_all_caches(struct amd_iommu *iommu);
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static inline int get_ioapic_devid(int id)
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{
@@ -1006,7 +1010,6 @@ struct amd_ir_data {
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struct irq_2_irte irq_2_irte;
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struct msi_msg msi_entry;
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void *entry; /* Pointer to union irte or struct irte_ga */
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void *ref; /* Pointer to the actual irte */
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/**
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* Store information for activate/de-activate

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