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Merge tag 'mailbox-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
Pull mailbox updates from Jassi Brar: "broadcom: - remove unused pdc_dma_map imx: - fix TXDB_V2 channel race condition mediatek: - cleanup and refactor driver - add bindings for gce-props omap: - fix mailbox interrupt sharing qcom: - add bindings for SA8775p - add CPUCP driver zynqmp: - make polling period configurable" * tag 'mailbox-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: mailbox: mtk-cmdq: Move devm_mbox_controller_register() after devm_pm_runtime_enable() mailbox: zynqmp-ipi: Make polling period configurable mailbox: qcom-cpucp: fix 64BIT dependency mailbox: Add support for QTI CPUCP mailbox controller dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings dt-bindings: remoteproc: qcom,sa8775p-pas: Document the SA8775p ADSP, CDSP and GPDSP mailbox: mtk-cmdq: add missing MODULE_DESCRIPTION() macro mailbox: bcm-pdc: remove unused struct 'pdc_dma_map' mailbox: imx: fix TXDB_V2 channel race condition mailbox: omap: Fix mailbox interrupt sharing mailbox: mtk-cmdq: Dynamically allocate clk_bulk_data structure mailbox: mtk-cmdq: Move and partially refactor clocks probe mailbox: mtk-cmdq: Stop requiring name for GCE clock dt-bindings: mailbox: Add mediatek,gce-props.yaml
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‎Documentation/devicetree/bindings/mailbox/mediatek,gce-props.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Global Command Engine Common Properties
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maintainers:
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- Houlong Wei <[email protected]>
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description:
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The Global Command Engine (GCE) is an instruction based, multi-threaded,
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single-core command dispatcher for MediaTek hardware. The Command Queue
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(CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
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mailbox framework. It is used to receive messages from mailbox consumers
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and configure GCE to execute the specified instruction set in the message.
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We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
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driver. A device driver that uses the CMDQ driver to configure its hardware
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registers is a mailbox consumer. The mailbox consumer can request a mailbox
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channel corresponding to a GCE hardware thread to send a message, specifying
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that the GCE thread to configure its hardware. The mailbox provider can also
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reserve a mailbox channel to configure GCE hardware register by the specific
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GCE thread. This binding defines the common GCE properties for both mailbox
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provider and consumers.
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properties:
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mediatek,gce-events:
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description:
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GCE has an event table in SRAM, consisting of 1024 event IDs (0~1023).
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Each event ID has a boolean event value with the default value 0.
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The property mediatek,gce-events is used to obtain the event IDs.
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Some gce-events are hardware-bound and cannot be changed by software.
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For instance, in MT8195, when VDO0_MUTEX is stream done, VDO_MUTEX will
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send an event signal to GCE, setting the value of event ID 597 to 1.
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Similarly, in MT8188, the value of event ID 574 will be set to 1 when
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VOD0_MUTEX is stream done.
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On the other hand, some gce-events are not hardware-bound and can be
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changed by software. For example, in MT8188, we can set the value of
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event ID 855, which is not bound to any hardware, to 1 when the driver
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in the secure world completes a task. However, in MT8195, event ID 855
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is already bound to VDEC_LAT1, so we need to select another event ID to
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achieve the same purpose. This event ID can be any ID that is not bound
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to any hardware and is not yet used in any software driver.
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To determine if the event ID is bound to the hardware or used by a
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software driver, refer to the GCE header
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include/dt-bindings/gce/<chip>-gce.h of each chip.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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additionalProperties: true

‎Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml‎

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
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maintainers:
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- Sibi Sankar <[email protected]>
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description:
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The CPUSS Control Processor (CPUCP) mailbox controller enables communication
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between AP and CPUCP by acting as a doorbell between them.
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properties:
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compatible:
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items:
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- const: qcom,x1e80100-cpucp-mbox
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reg:
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items:
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- description: CPUCP rx register region
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- description: CPUCP tx register region
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interrupts:
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maxItems: 1
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"#mbox-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- "#mbox-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mailbox@17430000 {
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compatible = "qcom,x1e80100-cpucp-mbox";
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reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};

‎Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml‎

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/remoteproc/qcom,sa8775p-pas.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SA8775p Peripheral Authentication Service
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maintainers:
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- Bartosz Golaszewski <[email protected]>
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description:
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Qualcomm SA8775p SoC Peripheral Authentication Service loads and boots firmware
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on the Qualcomm DSP Hexagon cores.
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properties:
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compatible:
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enum:
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- qcom,sa8775p-adsp-pas
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- qcom,sa8775p-cdsp0-pas
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- qcom,sa8775p-cdsp1-pas
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- qcom,sa8775p-gpdsp0-pas
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- qcom,sa8775p-gpdsp1-pas
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reg:
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maxItems: 1
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clocks:
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items:
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- description: XO clock
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clock-names:
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items:
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- const: xo
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qcom,qmp:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Reference to the AOSS side-channel message RAM.
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firmware-name:
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$ref: /schemas/types.yaml#/definitions/string-array
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items:
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- description: Firmware name of the Hexagon core
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memory-region:
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items:
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- description: Memory region for main Firmware authentication
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interrupts:
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maxItems: 5
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interrupt-names:
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maxItems: 5
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required:
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- compatible
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- reg
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- memory-region
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allOf:
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- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
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- if:
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properties:
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compatible:
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enum:
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- qcom,sa8775p-adsp-pas
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then:
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properties:
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power-domains:
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items:
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- description: LCX power domain
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- description: LMX power domain
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power-domain-names:
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items:
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- const: lcx
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- const: lmx
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- if:
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properties:
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compatible:
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enum:
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- qcom,sa8775p-cdsp0-pas
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- qcom,sa8775p-cdsp1-pas
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then:
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properties:
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power-domains:
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items:
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- description: CX power domain
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- description: MXC power domain
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- description: NSP0 power domain
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power-domain-names:
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items:
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- const: cx
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- const: mxc
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- const: nsp
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- if:
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properties:
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compatible:
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enum:
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- qcom,sa8775p-gpdsp0-pas
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- qcom,sa8775p-gpdsp1-pas
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then:
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properties:
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power-domains:
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items:
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- description: CX power domain
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- description: MXC power domain
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power-domain-names:
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items:
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- const: cx
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- const: mxc
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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remoteproc@30000000 {
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compatible = "qcom,sa8775p-adsp-pas";
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reg = <0x30000000 0x100>;
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interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
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<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd RPMHPD_LCX>, <&rpmhpd RPMHPD_LMX>;
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power-domain-names = "lcx", "lmx";
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interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
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memory-region = <&pil_adsp_mem>;
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qcom,qmp = <&aoss_qmp>;
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qcom,smem-states = <&smp2p_adsp_out 0>;
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qcom,smem-state-names = "stop";
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glink-edge {
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
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label = "lpass";
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qcom,remote-pid = <2>;
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};
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};

‎MAINTAINERS‎

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F: Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
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F: drivers/pmdomain/qcom/cpr.c
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QUALCOMM CPUCP MAILBOX DRIVER
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M: Sibi Sankar <[email protected]>
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L: [email protected]
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S: Supported
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F: Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
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F: drivers/mailbox/qcom-cpucp-mbox.c
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1875218759
QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
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M: Ilia Lin <[email protected]>
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L: [email protected]

‎drivers/mailbox/Kconfig‎

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to send message between application processors and MCU. Say Y here if
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you want to build the Spreatrum mailbox controller driver.
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config QCOM_CPUCP_MBOX
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tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
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depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT
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help
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Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
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controller driver enables communication between AP and CPUCP. Say
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Y here if you want to build this driver.
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config QCOM_IPCC
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tristate "Qualcomm Technologies, Inc. IPCC driver"
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depends on ARCH_QCOM || COMPILE_TEST

‎drivers/mailbox/Makefile‎

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obj-$(CONFIG_SPRD_MBOX) += sprd-mailbox.o
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obj-$(CONFIG_QCOM_CPUCP_MBOX) += qcom-cpucp-mbox.o
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obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o

‎drivers/mailbox/bcm-pdc-mailbox.c‎

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PDC_HW /* PDC/MDE hardware (i.e. Northstar 2, Pegasus) */
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};
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struct pdc_dma_map {
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void *ctx; /* opaque context associated with frame */
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};
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/* dma descriptor */
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struct dma64dd {
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u32 ctrl1; /* misc control bits */

‎drivers/mailbox/imx-mailbox.c‎

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void *data)
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{
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u32 *arg = data;
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u32 val;
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int ret;
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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queue_work(system_bh_wq, &cp->txdb_work);
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break;
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case IMX_MU_TYPE_TXDB_V2:
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imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
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imx_mu_write(priv, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx),
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priv->dcfg->xCR[IMX_MU_GCR]);
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ret = readl_poll_timeout(priv->base + priv->dcfg->xCR[IMX_MU_GCR], val,
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!(val & IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx)),
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0, 1000);
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if (ret)
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dev_warn_ratelimited(priv->dev, "channel type: %d failure\n", cp->type);
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break;
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default:
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);

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