6363#define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0
6464#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0)
6565#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0
66+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K 1
67+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K 2
68+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K 3
69+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K 4
6670#define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248)
6771#define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264)
6872#define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268)
@@ -407,6 +411,7 @@ struct wsa_macro {
407411 int ear_spkr_gain ;
408412 int spkr_gain_offset ;
409413 int spkr_mode ;
414+ u32 pcm_rate_vi ;
410415 int is_softclip_on [WSA_MACRO_SOFTCLIP_MAX ];
411416 int softclip_clk_users [WSA_MACRO_SOFTCLIP_MAX ];
412417 struct regmap * regmap ;
@@ -1280,6 +1285,7 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
12801285 struct snd_soc_dai * dai )
12811286{
12821287 struct snd_soc_component * component = dai -> component ;
1288+ struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
12831289 int ret ;
12841290
12851291 switch (substream -> stream ) {
@@ -1291,6 +1297,11 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
12911297 __func__ , params_rate (params ));
12921298 return ret ;
12931299 }
1300+ break ;
1301+ case SNDRV_PCM_STREAM_CAPTURE :
1302+ if (dai -> id == WSA_MACRO_AIF_VI )
1303+ wsa -> pcm_rate_vi = params_rate (params );
1304+
12941305 break ;
12951306 default :
12961307 break ;
@@ -1465,6 +1476,28 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
14651476 struct snd_soc_component * component = snd_soc_dapm_to_component (w -> dapm );
14661477 struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
14671478 u32 tx_reg0 , tx_reg1 ;
1479+ u32 rate_val ;
1480+
1481+ switch (wsa -> pcm_rate_vi ) {
1482+ case 8000 :
1483+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K ;
1484+ break ;
1485+ case 16000 :
1486+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K ;
1487+ break ;
1488+ case 24000 :
1489+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K ;
1490+ break ;
1491+ case 32000 :
1492+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K ;
1493+ break ;
1494+ case 48000 :
1495+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K ;
1496+ break ;
1497+ default :
1498+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K ;
1499+ break ;
1500+ }
14681501
14691502 if (test_bit (WSA_MACRO_TX0 , & wsa -> active_ch_mask [WSA_MACRO_AIF_VI ])) {
14701503 tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL ;
@@ -1476,7 +1509,7 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
14761509
14771510 switch (event ) {
14781511 case SND_SOC_DAPM_POST_PMU :
1479- /* Enable V&I sensing */
1512+ /* Enable V&I sensing */
14801513 snd_soc_component_update_bits (component , tx_reg0 ,
14811514 CDC_WSA_TX_SPKR_PROT_RESET_MASK ,
14821515 CDC_WSA_TX_SPKR_PROT_RESET );
@@ -1485,10 +1518,10 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
14851518 CDC_WSA_TX_SPKR_PROT_RESET );
14861519 snd_soc_component_update_bits (component , tx_reg0 ,
14871520 CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK ,
1488- CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K );
1521+ rate_val );
14891522 snd_soc_component_update_bits (component , tx_reg1 ,
14901523 CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK ,
1491- CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K );
1524+ rate_val );
14921525 snd_soc_component_update_bits (component , tx_reg0 ,
14931526 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK ,
14941527 CDC_WSA_TX_SPKR_PROT_CLK_ENABLE );
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