Merge tag 'riscv-mw1-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next

riscv patches for 6.15-rc1

* A bunch of fixes:
  - We were missing a secondary mmu notifier call when flushing the tlb which is required for IOMMU
  - Fix ftrace panics by saving the registers as expected by ftrace
  - Fix a couple of stimecmp usage related to cpu hotplug
  - Fix a bunch of issues in the misaligned probing handling

* Perf improvements:
  - Introduce support for runtime constant improving perf of d_hash()
  - Add support for huge pfnmaps to improve tlb utilization
  - Use Zawrs to improve smp_cond_load8/16() used by the queued spinlocks

* Hwprobe additions:
  - Add support for Zicntr and Zihpm
  - Add support for Zaamo and Zalrsc
  - Add support for bfloat16 extensiosn
  - Add support for Zicbom (only enabling clean and flush, not inval for security reasons)

* Misc:
  - Add a kernel parameter to bypass the misaligned speed probing since we can't rely on Zicclsm

* tag 'riscv-mw1-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux: (1585 commits)
  riscv: Add runtime constant support
  riscv: Move nop definition to insn-def.h
  Documentation/kernel-parameters: Add riscv unaligned speed parameters
  riscv: Add parameter for skipping access speed tests
  riscv: Fix set up of vector cpu hotplug callback
  riscv: Fix set up of cpu hotplug callbacks
  riscv: Change check_unaligned_access_speed_all_cpus to void
  riscv: Fix check_unaligned_access_all_cpus
  riscv: Fix riscv_online_cpu_vec
  riscv: Annotate unaligned access init functions
  KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test
  RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM
  riscv: hwprobe: export Zaamo and Zalrsc extensions
  riscv: add parsing for Zaamo and Zalrsc extensions
  dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description
  riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of ftrace_return_to_handler
  riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on HAVE_DYNAMIC_FTRACE_WITH_ARGS
  riscv: Fix missing __free_pages() in check_vector_unaligned_access()
  riscv: Fix the __riscv_copy_vec_words_unaligned implementation
  riscv: mm: Don't use %pK through printk
  ...

Author: palmer-dabbelt

.mailmap

@@ -88,7 +88,6 @@ Antonio Quartulli <[email protected]> <[email protected]>
 Antonio Quartulli <[email protected]> <[email protected]>
 Antonio Quartulli <[email protected]> <[email protected]>
 Antonio Quartulli <[email protected]> <[email protected]>
-Antonio Quartulli <[email protected]> <[email protected]>
 Antonio Quartulli <[email protected]> <[email protected]>
 Anup Patel <[email protected]> <[email protected]>
 Archit Taneja <[email protected]>
@@ -226,6 +225,7 @@ Fangrui Song <[email protected]> <[email protected]>
 Felipe W Damasio <[email protected]>
 Felix Kuhling <[email protected]>
 Felix Moeller <[email protected]>
+Feng Tang <[email protected]> <[email protected]>
 Fenglin Wu <[email protected]> <[email protected]>
 Filipe Lautert <[email protected]>
 Finn Thain <[email protected]> <[email protected]>
@@ -281,6 +281,7 @@ Henrik Rydberg <[email protected]>
 Herbert Xu <[email protected]>
 Huacai Chen <[email protected]> <[email protected]>
 Huacai Chen <[email protected]> <[email protected]>
+Ike Panhc <[email protected]> <[email protected]>
 J. Bruce Fields <[email protected]> <[email protected]>
 J. Bruce Fields <[email protected]> <[email protected]>
 Jacob Shin <[email protected]>
@@ -317,6 +318,8 @@ Jayachandran C <[email protected]> <[email protected]>
 Jean Tourrilhes <[email protected]>
 Jeevan Shriram <[email protected]> <[email protected]>
 Jeff Garzik <[email protected]>
+Jeff Johnson <[email protected]> <[email protected]>
+Jeff Johnson <[email protected]> <[email protected]>
 Jeff Layton <[email protected]> <[email protected]>
 Jeff Layton <[email protected]> <[email protected]>
 Jeff Layton <[email protected]> <[email protected]>
@@ -376,6 +379,7 @@ Juha Yrjola <[email protected]>
 Julien Thierry <[email protected]> <[email protected]>
 Iskren Chernev <[email protected]> <[email protected]>
 Kalle Valo <[email protected]> <[email protected]>
+Kalle Valo <[email protected]> <[email protected]>
 Kalyan Thota <[email protected]> <[email protected]>
 Karthikeyan Periyasamy <[email protected]> <[email protected]>
 Kathiravan T <[email protected]> <[email protected]>
@@ -518,6 +522,7 @@ Nadav Amit <[email protected]> <[email protected]>
 Nadia Yvette Chambers <[email protected]> William Lee Irwin III <[email protected]>
 Naoya Horiguchi <[email protected]> <[email protected]>
 Naoya Horiguchi <[email protected]> <[email protected]>
+Natalie Vock <[email protected]> <[email protected]>
 Nathan Chancellor <[email protected]> <[email protected]>
 Naveen N Rao <[email protected]> <[email protected]>
 Naveen N Rao <[email protected]> <[email protected]>
@@ -530,6 +535,7 @@ Nicholas Piggin <[email protected]> <[email protected]>
 Nicholas Piggin <[email protected]> <[email protected]>
 Nicholas Piggin <[email protected]> <[email protected]>
 Nicholas Piggin <[email protected]> <[email protected]>
+Nick Desaulniers <[email protected]> <[email protected]>
 Nicolas Ferre <[email protected]> <[email protected]>
 Nicolas Pitre <[email protected]> <[email protected]>
 Nicolas Pitre <[email protected]> <[email protected]>
@@ -608,6 +614,8 @@ Richard Leitner <[email protected]> <[email protected]>
 Richard Leitner <[email protected]> <[email protected]>
 Robert Foss <[email protected]> <[email protected]>
 Rocky Liao <[email protected]> <[email protected]>
+Rodrigo Siqueira <[email protected]> <[email protected]>
+Rodrigo Siqueira <[email protected]> <[email protected]>
 Roman Gushchin <[email protected]> <[email protected]>
 Roman Gushchin <[email protected]> <[email protected]>
 Roman Gushchin <[email protected]> <[email protected]>
@@ -684,6 +692,7 @@ Subbaraman Narayanamurthy <[email protected]> <[email protected]>
 Subhash Jadavani <[email protected]>
 Sudarshan Rajagopalan <[email protected]> <[email protected]>
 Sudeep Holla <[email protected]> Sudeep KarkadaNagesha <[email protected]>
+Sumit Garg <[email protected]> <[email protected]>
 Sumit Semwal <[email protected]>
 Surabhi Vishnoi <[email protected]> <[email protected]>
 Sven Eckelmann <[email protected]> <[email protected]>

CREDITS

@@ -2515,11 +2515,9 @@ D: SLS distribution
 D: Initial implementation of VC's, pty's and select()
 
 N: Pavel Machek
-E: pavel@ucw.cz
+E: pavel@kernel.org
 P: 4096R/92DFCE96 4FA7 9EEF FCD4 C44F C585  B8C7 C060 2241 92DF CE96
-D: Softcursor for vga, hypertech cdrom support, vcsa bugfix, nbd,
-D: sun4/330 port, capabilities for elf, speedup for rm on ext2, USB,
-D: work on suspend-to-ram/disk, killing duplicates from ioctl32,
+D: NBD, Sun4/330 port, USB, work on suspend-to-ram/disk,
 D: Altera SoCFPGA and Nokia N900 support.
 S: Czech Republic
 

Documentation/admin-guide/README.rst

@@ -176,7 +176,7 @@ Configuring the kernel
                         values without prompting.
 
      "make defconfig"   Create a ./.config file by using the default
-                        symbol values from either arch/$ARCH/defconfig
+                        symbol values from either arch/$ARCH/configs/defconfig
                         or arch/$ARCH/configs/${PLATFORM}_defconfig,
                         depending on the architecture.
 

Documentation/admin-guide/kernel-parameters.txt

@@ -7477,6 +7477,22 @@
 			Note that genuine overcurrent events won't be
 			reported either.
 
+	unaligned_scalar_speed=
+			[RISCV]
+			Format: {slow | fast | unsupported}
+			Allow skipping scalar unaligned access speed tests. This
+			is useful for testing alternative code paths and to skip
+			the tests in environments where they run too slowly. All
+			CPUs must have the same scalar unaligned access speed.
+
+	unaligned_vector_speed=
+			[RISCV]
+			Format: {slow | fast | unsupported}
+			Allow skipping vector unaligned access speed tests. This
+			is useful for testing alternative code paths and to skip
+			the tests in environments where they run too slowly. All
+			CPUs must have the same vector unaligned access speed.
+
 	unknown_nmi_panic
 			[X86] Cause panic on unknown NMI.
 

Documentation/admin-guide/sysctl/kernel.rst

@@ -212,6 +212,17 @@ pid>/``).
 This value defaults to 0.
 
 
+core_sort_vma
+=============
+
+The default coredump writes VMAs in address order. By setting
+``core_sort_vma`` to 1, VMAs will be written from smallest size
+to largest size. This is known to break at least elfutils, but
+can be handy when dealing with very large (and truncated)
+coredumps where the more useful debugging details are included
+in the smaller VMAs.
+
+
 core_uses_pid
 =============
 

Documentation/arch/arm64/gcs.rst

@@ -37,7 +37,7 @@ intended to be exhaustive.
   shadow stacks rather than GCS.
 
 * Support for GCS is reported to userspace via HWCAP_GCS in the aux vector
-  AT_HWCAP2 entry.
+  AT_HWCAP entry.
 
 * GCS is enabled per thread.  While there is support for disabling GCS
   at runtime this should be done with great care.

Documentation/arch/powerpc/cxl.rst

@@ -18,6 +18,7 @@ Introduction
     both access system memory directly and with the same effective
     addresses.
 
+    **This driver is deprecated and will be removed in a future release.**
 
 Hardware overview
 =================
@@ -453,7 +454,7 @@ Sysfs Class
 
     A cxl sysfs class is added under /sys/class/cxl to facilitate
     enumeration and tuning of the accelerators. Its layout is
-    described in Documentation/ABI/testing/sysfs-class-cxl
+    described in Documentation/ABI/obsolete/sysfs-class-cxl
 
 
 Udev rules

Documentation/arch/riscv/hwprobe.rst

@@ -183,6 +183,9 @@ The following keys are defined:
        defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
        from commit 5059e0ca641c ("update to ratified").
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0
+       is supported as defined in the RISC-V ISA manual.
+
   * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
        defined in the RISC-V Integer Conditional (Zicond) operations extension
        manual starting from commit 95cf1f9 ("Add changes requested by Ved
@@ -192,6 +195,9 @@ The following keys are defined:
        supported as defined in the RISC-V ISA manual starting from commit
        d8ab5c78c207 ("Zihintpause is ratified").
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0
+       is supported as defined in the RISC-V ISA manual.
+
   * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
     supported, as defined by version 1.0 of the RISC-V Vector extension manual.
 
@@ -239,9 +245,32 @@ The following keys are defined:
        ratified in commit 98918c844281 ("Merge pull request #1217 from
        riscv/zawrs") of riscv-isa-manual.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as
+       defined in the in the RISC-V ISA manual starting from commit e87412e621f1
+       ("integrate Zaamo and Zalrsc text (#1304)").
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
+       defined in the in the RISC-V ISA manual starting from commit e87412e621f1
+       ("integrate Zaamo and Zalrsc text (#1304)").
+
   * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
        defined in version 1.0 of the RISC-V Pointer Masking extensions.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
+       defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+       ("Added Chapter title to BF16").
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
+       defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+       ("Added Chapter title to BF16").
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
+       defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+       ("Added Chapter title to BF16").
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
+       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
      :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
      mistakenly classified as a bitmask rather than a value.
@@ -303,3 +332,6 @@ The following keys are defined:
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor
         extension is supported in the T-Head ISA extensions spec starting from
 	commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
+
+* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
+  represents the size of the Zicbom block in bytes.

Documentation/arch/x86/sva.rst

@@ -25,7 +25,7 @@ to cache translations for virtual addresses. The IOMMU driver uses the
 mmu_notifier() support to keep the device TLB cache and the CPU cache in
 sync. When an ATS lookup fails for a virtual address, the device should
 use the PRI in order to request the virtual address to be paged into the
-CPU page tables. The device must use ATS again in order the fetch the
+CPU page tables. The device must use ATS again in order to fetch the
 translation before use.
 
 Shared Hardware Workqueues
@@ -216,7 +216,7 @@ submitting work and processing completions.
 
 Single Root I/O Virtualization (SR-IOV) focuses on providing independent
 hardware interfaces for virtualizing hardware. Hence, it's required to be
-almost fully functional interface to software supporting the traditional
+an almost fully functional interface to software supporting the traditional
 BARs, space for interrupts via MSI-X, its own register layout.
 Virtual Functions (VFs) are assisted by the Physical Function (PF)
 driver.

Documentation/devicetree/bindings/arm/rockchip/pmu.yaml

@@ -53,11 +53,17 @@ properties:
   reg:
     maxItems: 1
 
+  power-controller:
+    type: object
+
+  reboot-mode:
+    type: object
+
 required:
   - compatible
   - reg
 
-additionalProperties: true
+additionalProperties: false
 
 examples:
   - |