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Merge tag 'v6.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stübner: - Get rid of CLK_NR_CLKS defines in Rockchip DT binding headers - New clock controller driver for the rk3576 - Some fixes for rk3228 and rk3588 * tag 'v6.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: rk3368: Drop CLK_NR_CLKS usage clk: rockchip: rk3328: Drop CLK_NR_CLKS usage clk: rockchip: rk3308: Drop CLK_NR_CLKS usage clk: rockchip: rk3288: Drop CLK_NR_CLKS usage clk: rockchip: rk3228: Drop CLK_NR_CLKS usage clk: rockchip: rk3036: Drop CLK_NR_CLKS usage clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228
2 parents 8400291 + 12fd64b commit df947ad

28 files changed

+3794
-78
lines changed

‎Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip rk3576 Family Clock and Reset Control Module
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9+
maintainers:
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- Elaine Zhang <[email protected]>
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- Heiko Stuebner <[email protected]>
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- Detlev Casanova <[email protected]>
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description:
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The RK3576 clock controller generates the clock and also implements a reset
16+
controller for SoC peripherals. For example it provides SCLK_UART2 and
17+
PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
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module.
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20+
properties:
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compatible:
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const: rockchip,rk3576-cru
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24+
reg:
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maxItems: 1
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27+
"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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clocks:
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maxItems: 2
35+
36+
clock-names:
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items:
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- const: xin24m
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- const: xin32k
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required:
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- compatible
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- reg
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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clock-controller@27200000 {
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compatible = "rockchip,rk3576-cru";
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reg = <0xfd7c0000 0x5c000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
56+
};

‎Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -42,10 +42,6 @@ properties:
4242
- const: xin24m
4343
- const: xin32k
4444

45-
assigned-clocks: true
46-
47-
assigned-clock-rates: true
48-
4945
rockchip,grf:
5046
$ref: /schemas/types.yaml#/definitions/phandle
5147
description: >

‎drivers/clk/rockchip/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -100,6 +100,13 @@ config CLK_RK3568
100100
help
101101
Build the driver for RK3568 Clock Driver.
102102

103+
config CLK_RK3576
104+
bool "Rockchip RK3576 clock controller support"
105+
depends on ARM64 || COMPILE_TEST
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default y
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help
108+
Build the driver for RK3576 Clock Driver.
109+
103110
config CLK_RK3588
104111
bool "Rockchip RK3588 clock controller support"
105112
depends on ARM64 || COMPILE_TEST

‎drivers/clk/rockchip/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,4 +28,5 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
2828
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
2929
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
3030
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
31+
obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o
3132
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o

‎drivers/clk/rockchip/clk-pll.c‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned
914914
}
915915
rate64 = rate64 >> cur.s;
916916

917-
return (unsigned long)rate64;
917+
if (pll->type == pll_rk3588_ddr)
918+
return (unsigned long)rate64 * 2;
919+
else
920+
return (unsigned long)rate64;
918921
}
919922

920923
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
@@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
11671170
break;
11681171
case pll_rk3588:
11691172
case pll_rk3588_core:
1173+
case pll_rk3588_ddr:
11701174
if (!pll->rate_table)
11711175
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
11721176
else

‎drivers/clk/rockchip/clk-px30.c‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1002,6 +1002,7 @@ static const char *const px30_cru_critical_clocks[] __initconst = {
10021002
static void __init px30_clk_init(struct device_node *np)
10031003
{
10041004
struct rockchip_clk_provider *ctx;
1005+
unsigned long clk_nr_clks;
10051006
void __iomem *reg_base;
10061007

10071008
reg_base = of_iomap(np, 0);
@@ -1010,7 +1011,9 @@ static void __init px30_clk_init(struct device_node *np)
10101011
return;
10111012
}
10121013

1013-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1014+
clk_nr_clks = rockchip_clk_find_max_clk_id(px30_clk_branches,
1015+
ARRAY_SIZE(px30_clk_branches)) + 1;
1016+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
10141017
if (IS_ERR(ctx)) {
10151018
pr_err("%s: rockchip clk init failed\n", __func__);
10161019
iounmap(reg_base);
@@ -1043,6 +1046,7 @@ CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
10431046
static void __init px30_pmu_clk_init(struct device_node *np)
10441047
{
10451048
struct rockchip_clk_provider *ctx;
1049+
unsigned long clkpmu_nr_clks;
10461050
void __iomem *reg_base;
10471051

10481052
reg_base = of_iomap(np, 0);
@@ -1051,7 +1055,9 @@ static void __init px30_pmu_clk_init(struct device_node *np)
10511055
return;
10521056
}
10531057

1054-
ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1058+
clkpmu_nr_clks = rockchip_clk_find_max_clk_id(px30_clk_pmu_branches,
1059+
ARRAY_SIZE(px30_clk_pmu_branches)) + 1;
1060+
ctx = rockchip_clk_init(np, reg_base, clkpmu_nr_clks);
10551061
if (IS_ERR(ctx)) {
10561062
pr_err("%s: rockchip pmu clk init failed\n", __func__);
10571063
return;

‎drivers/clk/rockchip/clk-rk3036.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -436,6 +436,7 @@ static const char *const rk3036_critical_clocks[] __initconst = {
436436
static void __init rk3036_clk_init(struct device_node *np)
437437
{
438438
struct rockchip_clk_provider *ctx;
439+
unsigned long clk_nr_clks;
439440
void __iomem *reg_base;
440441
struct clk *clk;
441442

@@ -452,7 +453,9 @@ static void __init rk3036_clk_init(struct device_node *np)
452453
writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
453454
reg_base + RK2928_CLKSEL_CON(13));
454455

455-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
456+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3036_clk_branches,
457+
ARRAY_SIZE(rk3036_clk_branches)) + 1;
458+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
456459
if (IS_ERR(ctx)) {
457460
pr_err("%s: rockchip clk init failed\n", __func__);
458461
iounmap(reg_base);

‎drivers/clk/rockchip/clk-rk3228.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
409409
RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
410410
DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
411411
RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
412-
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
412+
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
413413
RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
414414

415415
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
@@ -683,6 +683,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
683683
static void __init rk3228_clk_init(struct device_node *np)
684684
{
685685
struct rockchip_clk_provider *ctx;
686+
unsigned long clk_nr_clks;
686687
void __iomem *reg_base;
687688

688689
reg_base = of_iomap(np, 0);
@@ -691,7 +692,9 @@ static void __init rk3228_clk_init(struct device_node *np)
691692
return;
692693
}
693694

694-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
695+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3228_clk_branches,
696+
ARRAY_SIZE(rk3228_clk_branches)) + 1;
697+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
695698
if (IS_ERR(ctx)) {
696699
pr_err("%s: rockchip clk init failed\n", __func__);
697700
iounmap(reg_base);

‎drivers/clk/rockchip/clk-rk3288.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -932,14 +932,17 @@ static void __init rk3288_common_init(struct device_node *np,
932932
enum rk3288_variant soc)
933933
{
934934
struct rockchip_clk_provider *ctx;
935+
unsigned long clk_nr_clks;
935936

936937
rk3288_cru_base = of_iomap(np, 0);
937938
if (!rk3288_cru_base) {
938939
pr_err("%s: could not map cru region\n", __func__);
939940
return;
940941
}
941942

942-
ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
943+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3288_clk_branches,
944+
ARRAY_SIZE(rk3288_clk_branches)) + 1;
945+
ctx = rockchip_clk_init(np, rk3288_cru_base, clk_nr_clks);
943946
if (IS_ERR(ctx)) {
944947
pr_err("%s: rockchip clk init failed\n", __func__);
945948
iounmap(rk3288_cru_base);

‎drivers/clk/rockchip/clk-rk3308.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -917,6 +917,7 @@ static const char *const rk3308_critical_clocks[] __initconst = {
917917
static void __init rk3308_clk_init(struct device_node *np)
918918
{
919919
struct rockchip_clk_provider *ctx;
920+
unsigned long clk_nr_clks;
920921
void __iomem *reg_base;
921922

922923
reg_base = of_iomap(np, 0);
@@ -925,7 +926,9 @@ static void __init rk3308_clk_init(struct device_node *np)
925926
return;
926927
}
927928

928-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
929+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3308_clk_branches,
930+
ARRAY_SIZE(rk3308_clk_branches)) + 1;
931+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
929932
if (IS_ERR(ctx)) {
930933
pr_err("%s: rockchip clk init failed\n", __func__);
931934
iounmap(reg_base);

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