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clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks
In case of all pipe clocks, there is a QMP PHY clock that is feeding them. If, for whatever reason, the clock from the PHY is not enabled, halt bit will not get set, and the clock controller driver will assume the clock is stuck in a specific state. The way this is supposed to be properly fixed is to defer the checking of the halt bit until after the PHY clock has been initialized, but doing so complicates the clock controller driver. In fact, since these pipe clocks are consumed by the PHY, while the PHY is also the one providing the source, if clock gets stuck, the PHY driver would be to blame. So instead of checking the halt bit in here, just skip it and assume the PHY driver is handling the source clock correctly. Fixes: 161b7c4 ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Taniya Das <[email protected]> Link: https://lore.kernel.org/r/20240628-x1e80100-clk-gcc-fix-halt-check-for-usb-phy-pipe-clks-v2-1-db3be54b1143@linaro.org Signed-off-by: Bjorn Andersson <[email protected]>
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‎drivers/clk/qcom/gcc-x1e80100.c‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -2812,7 +2812,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
28122812

28132813
static struct clk_branch gcc_pcie_0_pipe_clk = {
28142814
.halt_reg = 0xa0044,
2815-
.halt_check = BRANCH_HALT_VOTED,
2815+
.halt_check = BRANCH_HALT_SKIP,
28162816
.clkr = {
28172817
.enable_reg = 0x52010,
28182818
.enable_mask = BIT(25),
@@ -2901,7 +2901,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
29012901

29022902
static struct clk_branch gcc_pcie_1_pipe_clk = {
29032903
.halt_reg = 0x2c044,
2904-
.halt_check = BRANCH_HALT_VOTED,
2904+
.halt_check = BRANCH_HALT_SKIP,
29052905
.clkr = {
29062906
.enable_reg = 0x52020,
29072907
.enable_mask = BIT(30),
@@ -2990,7 +2990,7 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
29902990

29912991
static struct clk_branch gcc_pcie_2_pipe_clk = {
29922992
.halt_reg = 0x13044,
2993-
.halt_check = BRANCH_HALT_VOTED,
2993+
.halt_check = BRANCH_HALT_SKIP,
29942994
.clkr = {
29952995
.enable_reg = 0x52020,
29962996
.enable_mask = BIT(23),
@@ -3110,7 +3110,7 @@ static struct clk_branch gcc_pcie_3_phy_rchng_clk = {
31103110

31113111
static struct clk_branch gcc_pcie_3_pipe_clk = {
31123112
.halt_reg = 0x58050,
3113-
.halt_check = BRANCH_HALT_VOTED,
3113+
.halt_check = BRANCH_HALT_SKIP,
31143114
.clkr = {
31153115
.enable_reg = 0x52020,
31163116
.enable_mask = BIT(3),
@@ -3235,7 +3235,7 @@ static struct clk_branch gcc_pcie_4_phy_rchng_clk = {
32353235

32363236
static struct clk_branch gcc_pcie_4_pipe_clk = {
32373237
.halt_reg = 0x6b044,
3238-
.halt_check = BRANCH_HALT_VOTED,
3238+
.halt_check = BRANCH_HALT_SKIP,
32393239
.clkr = {
32403240
.enable_reg = 0x52008,
32413241
.enable_mask = BIT(4),
@@ -3360,7 +3360,7 @@ static struct clk_branch gcc_pcie_5_phy_rchng_clk = {
33603360

33613361
static struct clk_branch gcc_pcie_5_pipe_clk = {
33623362
.halt_reg = 0x2f044,
3363-
.halt_check = BRANCH_HALT_VOTED,
3363+
.halt_check = BRANCH_HALT_SKIP,
33643364
.clkr = {
33653365
.enable_reg = 0x52018,
33663366
.enable_mask = BIT(17),
@@ -3498,7 +3498,7 @@ static struct clk_branch gcc_pcie_6a_phy_rchng_clk = {
34983498

34993499
static struct clk_branch gcc_pcie_6a_pipe_clk = {
35003500
.halt_reg = 0x31050,
3501-
.halt_check = BRANCH_HALT_VOTED,
3501+
.halt_check = BRANCH_HALT_SKIP,
35023502
.clkr = {
35033503
.enable_reg = 0x52018,
35043504
.enable_mask = BIT(26),
@@ -3636,7 +3636,7 @@ static struct clk_branch gcc_pcie_6b_phy_rchng_clk = {
36363636

36373637
static struct clk_branch gcc_pcie_6b_pipe_clk = {
36383638
.halt_reg = 0x8d050,
3639-
.halt_check = BRANCH_HALT_VOTED,
3639+
.halt_check = BRANCH_HALT_SKIP,
36403640
.clkr = {
36413641
.enable_reg = 0x52000,
36423642
.enable_mask = BIT(30),
@@ -5109,7 +5109,7 @@ static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
51095109

51105110
static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
51115111
.halt_reg = 0x17290,
5112-
.halt_check = BRANCH_HALT,
5112+
.halt_check = BRANCH_HALT_SKIP,
51135113
.clkr = {
51145114
.enable_reg = 0x17290,
51155115
.enable_mask = BIT(0),
@@ -5122,7 +5122,7 @@ static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
51225122

51235123
static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
51245124
.halt_reg = 0x17298,
5125-
.halt_check = BRANCH_HALT,
5125+
.halt_check = BRANCH_HALT_SKIP,
51265126
.clkr = {
51275127
.enable_reg = 0x17298,
51285128
.enable_mask = BIT(0),
@@ -5186,7 +5186,7 @@ static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
51865186

51875187
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
51885188
.halt_reg = 0x39068,
5189-
.halt_check = BRANCH_HALT_VOTED,
5189+
.halt_check = BRANCH_HALT_SKIP,
51905190
.hwcg_reg = 0x39068,
51915191
.hwcg_bit = 1,
51925192
.clkr = {
@@ -5257,7 +5257,7 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
52575257

52585258
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
52595259
.halt_reg = 0xa1068,
5260-
.halt_check = BRANCH_HALT_VOTED,
5260+
.halt_check = BRANCH_HALT_SKIP,
52615261
.hwcg_reg = 0xa1068,
52625262
.hwcg_bit = 1,
52635263
.clkr = {
@@ -5327,7 +5327,7 @@ static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
53275327

53285328
static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
53295329
.halt_reg = 0xa2068,
5330-
.halt_check = BRANCH_HALT_VOTED,
5330+
.halt_check = BRANCH_HALT_SKIP,
53315331
.hwcg_reg = 0xa2068,
53325332
.hwcg_bit = 1,
53335333
.clkr = {
@@ -5405,7 +5405,7 @@ static struct clk_branch gcc_usb4_0_master_clk = {
54055405

54065406
static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
54075407
.halt_reg = 0x9f0d8,
5408-
.halt_check = BRANCH_HALT,
5408+
.halt_check = BRANCH_HALT_SKIP,
54095409
.clkr = {
54105410
.enable_reg = 0x9f0d8,
54115411
.enable_mask = BIT(0),
@@ -5418,7 +5418,7 @@ static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
54185418

54195419
static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
54205420
.halt_reg = 0x9f048,
5421-
.halt_check = BRANCH_HALT_VOTED,
5421+
.halt_check = BRANCH_HALT_SKIP,
54225422
.clkr = {
54235423
.enable_reg = 0x52010,
54245424
.enable_mask = BIT(19),
@@ -5457,7 +5457,7 @@ static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
54575457

54585458
static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
54595459
.halt_reg = 0x9f0a4,
5460-
.halt_check = BRANCH_HALT_VOTED,
5460+
.halt_check = BRANCH_HALT_SKIP,
54615461
.hwcg_reg = 0x9f0a4,
54625462
.hwcg_bit = 1,
54635463
.clkr = {
@@ -5582,7 +5582,7 @@ static struct clk_branch gcc_usb4_1_master_clk = {
55825582

55835583
static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
55845584
.halt_reg = 0x2b0d8,
5585-
.halt_check = BRANCH_HALT,
5585+
.halt_check = BRANCH_HALT_SKIP,
55865586
.clkr = {
55875587
.enable_reg = 0x2b0d8,
55885588
.enable_mask = BIT(0),
@@ -5595,7 +5595,7 @@ static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
55955595

55965596
static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
55975597
.halt_reg = 0x2b048,
5598-
.halt_check = BRANCH_HALT_VOTED,
5598+
.halt_check = BRANCH_HALT_SKIP,
55995599
.clkr = {
56005600
.enable_reg = 0x52028,
56015601
.enable_mask = BIT(0),
@@ -5634,7 +5634,7 @@ static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
56345634

56355635
static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
56365636
.halt_reg = 0x2b0a4,
5637-
.halt_check = BRANCH_HALT_VOTED,
5637+
.halt_check = BRANCH_HALT_SKIP,
56385638
.hwcg_reg = 0x2b0a4,
56395639
.hwcg_bit = 1,
56405640
.clkr = {
@@ -5759,7 +5759,7 @@ static struct clk_branch gcc_usb4_2_master_clk = {
57595759

57605760
static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
57615761
.halt_reg = 0x110d8,
5762-
.halt_check = BRANCH_HALT,
5762+
.halt_check = BRANCH_HALT_SKIP,
57635763
.clkr = {
57645764
.enable_reg = 0x110d8,
57655765
.enable_mask = BIT(0),
@@ -5772,7 +5772,7 @@ static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
57725772

57735773
static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
57745774
.halt_reg = 0x11048,
5775-
.halt_check = BRANCH_HALT_VOTED,
5775+
.halt_check = BRANCH_HALT_SKIP,
57765776
.clkr = {
57775777
.enable_reg = 0x52028,
57785778
.enable_mask = BIT(1),
@@ -5811,7 +5811,7 @@ static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
58115811

58125812
static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
58135813
.halt_reg = 0x110a4,
5814-
.halt_check = BRANCH_HALT_VOTED,
5814+
.halt_check = BRANCH_HALT_SKIP,
58155815
.hwcg_reg = 0x110a4,
58165816
.hwcg_bit = 1,
58175817
.clkr = {

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