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airliedairlied
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Merge tag 'amd-drm-fixes-6.14-2025-02-05' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.14-2025-02-05: amdgpu: - Add BO metadata flag for DCC - Fix potential out of bounds access in display - Seamless boot fix - CONFIG_FRAME_WARN fix - PSR1 fix UAPI: - Add new tiling flag for DCC write compress disable Proposed userspace: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33255 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 2014c95 + f245b40 commit f2e6f00

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18 files changed

+64
-33
lines changed

18 files changed

+64
-33
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,9 +119,10 @@
119119
* - 3.57.0 - Compute tunneling on GFX10+
120120
* - 3.58.0 - Add GFX12 DCC support
121121
* - 3.59.0 - Cleared VRAM
122+
* - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
122123
*/
123124
#define KMS_DRIVER_MAJOR 3
124-
#define KMS_DRIVER_MINOR 59
125+
#define KMS_DRIVER_MINOR 60
125126
#define KMS_DRIVER_PATCHLEVEL 0
126127

127128
/*

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -309,7 +309,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
309309
mutex_lock(&adev->mman.gtt_window_lock);
310310
while (src_mm.remaining) {
311311
uint64_t from, to, cur_size, tiling_flags;
312-
uint32_t num_type, data_format, max_com;
312+
uint32_t num_type, data_format, max_com, write_compress_disable;
313313
struct dma_fence *next;
314314

315315
/* Never copy more than 256MiB at once to avoid a timeout */
@@ -340,9 +340,13 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
340340
max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
341341
num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
342342
data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
343+
write_compress_disable =
344+
AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);
343345
copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |
344346
AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |
345-
AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format));
347+
AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |
348+
AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,
349+
write_compress_disable));
346350
}
347351

348352
r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,8 @@ struct amdgpu_copy_mem {
119119
#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
120120
#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8
121121
#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
122+
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14
123+
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1
122124

123125
#define AMDGPU_COPY_FLAGS_SET(field, value) \
124126
(((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)

‎drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1741,11 +1741,12 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
17411741
uint32_t byte_count,
17421742
uint32_t copy_flags)
17431743
{
1744-
uint32_t num_type, data_format, max_com;
1744+
uint32_t num_type, data_format, max_com, write_cm;
17451745

17461746
max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
17471747
data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);
17481748
num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);
1749+
write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1;
17491750

17501751
ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
17511752
SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
@@ -1762,7 +1763,7 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
17621763
if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
17631764
ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |
17641765
((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
1765-
((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |
1766+
((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) |
17661767
SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);
17671768
else
17681769
ib->ptr[ib->length_dw++] = 0;

‎drivers/gpu/drm/amd/display/dc/core/dc.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2133,7 +2133,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
21332133

21342134
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
21352135

2136-
if (context->stream_count > get_seamless_boot_stream_count(context) ||
2136+
if (get_seamless_boot_stream_count(context) == 0 ||
21372137
context->stream_count == 0) {
21382138
/* Must wait for no flips to be pending before doing optimize bw */
21392139
hwss_wait_for_no_pipes_pending(dc, context);

‎drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
6363

6464
bool should_use_dmub_lock(struct dc_link *link)
6565
{
66-
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
67-
link->psr_settings.psr_version == DC_PSR_VERSION_1)
66+
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
6867
return true;
6968

7069
if (link->replay_settings.replay_feature_enabled)

‎drivers/gpu/drm/amd/display/dc/dml/Makefile‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,15 @@ dml_ccflags := $(CC_FLAGS_FPU)
2929
dml_rcflags := $(CC_FLAGS_NO_FPU)
3030

3131
ifneq ($(CONFIG_FRAME_WARN),0)
32-
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
33-
frame_warn_flag := -Wframe-larger-than=3072
34-
else
35-
frame_warn_flag := -Wframe-larger-than=2048
36-
endif
32+
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
33+
frame_warn_limit := 3072
34+
else
35+
frame_warn_limit := 2048
36+
endif
37+
38+
ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
39+
frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
40+
endif
3741
endif
3842

3943
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)

‎drivers/gpu/drm/amd/display/dc/dml2/Makefile‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -28,15 +28,19 @@ dml2_ccflags := $(CC_FLAGS_FPU)
2828
dml2_rcflags := $(CC_FLAGS_NO_FPU)
2929

3030
ifneq ($(CONFIG_FRAME_WARN),0)
31-
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
32-
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
33-
frame_warn_flag := -Wframe-larger-than=4096
34-
else
35-
frame_warn_flag := -Wframe-larger-than=3072
36-
endif
37-
else
38-
frame_warn_flag := -Wframe-larger-than=2048
39-
endif
31+
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
32+
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
33+
frame_warn_limit := 4096
34+
else
35+
frame_warn_limit := 3072
36+
endif
37+
else
38+
frame_warn_limit := 2048
39+
endif
40+
41+
ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
42+
frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
43+
endif
4044
endif
4145

4246
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2

‎drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1017,7 +1017,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
10171017
if (disp_cfg_stream_location < 0)
10181018
disp_cfg_stream_location = dml_dispcfg->num_streams++;
10191019

1020-
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1020+
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
10211021
populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx);
10221022
adjust_dml21_hblank_timing_config_from_pipe_ctx(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, &context->res_ctx.pipe_ctx[stream_index]);
10231023
populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);
@@ -1042,7 +1042,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
10421042
if (disp_cfg_plane_location < 0)
10431043
disp_cfg_plane_location = dml_dispcfg->num_planes++;
10441044

1045-
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1045+
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
10461046

10471047
populate_dml21_surface_config_from_plane_state(in_dc, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->stream_status[stream_index].plane_states[plane_index]);
10481048
populate_dml21_plane_config_from_plane_state(dml_ctx, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->stream_status[stream_index].plane_states[plane_index], context, stream_index);

‎drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -786,7 +786,7 @@ static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *
786786
case SIGNAL_TYPE_DISPLAY_PORT_MST:
787787
case SIGNAL_TYPE_DISPLAY_PORT:
788788
out->OutputEncoder[location] = dml_dp;
789-
if (dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
789+
if (location < MAX_HPO_DP2_ENCODERS && dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
790790
out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;
791791
break;
792792
case SIGNAL_TYPE_EDP:
@@ -1343,7 +1343,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat
13431343
if (disp_cfg_stream_location < 0)
13441344
disp_cfg_stream_location = dml_dispcfg->num_timings++;
13451345

1346-
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1346+
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
13471347

13481348
populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);
13491349
populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2);
@@ -1383,7 +1383,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat
13831383
if (disp_cfg_plane_location < 0)
13841384
disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
13851385

1386-
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1386+
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
13871387

13881388
populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);
13891389
populate_dml_plane_cfg_from_plane_state(

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