Commit f33dca9
dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
The driver will be modified (in the next commits) to be able to specify
individual power domain IDs for each IP. The driver will still
support #power-domain-cells = <0>, thus, previous users are not
affected.
The #power-domain-cells = <1> has been instantiated only for RZ/G3S at
the moment, as individual platform clock drivers need to be adapted for
this to be supported on the rest of the SoCs.
Also, the description for #power-domain-cells is updated with links to
per-SoC power domain IDs.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Ulf Hansson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>1 parent 2d03ce9 commit f33dca9
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