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clk: renesas: rcar-gen4: Use FIELD_GET()
Improve readability by using the FIELD_GET() helper instead of open-coding the same operation, and by adding field definitions to get rid of hardcoded values. While at it, move register definitions that are only used inside the rcar-gen4-cpg.c source file out of the rcar-gen4-cpg.h header file. Add a "CPG_" prefix to SD0CKCR1. Add comments where appropriate. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/fb19ad829738f02effa340fa04c178a162d41202.1721648548.git.geert+renesas@glider.be
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drivers/clk/renesas/rcar-gen4-cpg.c

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,14 @@ static u32 cpg_mode __initdata;
5555
/* Fractional 8.25 PLL */
5656
#define CPG_PLLxCR0_NI8 GENMASK(27, 20) /* Integer mult. factor */
5757

58+
#define CPG_PLLxCR_STC GENMASK(30, 24) /* R_Car V3U PLLxCR */
59+
60+
#define CPG_RPCCKCR 0x874 /* RPC Clock Freq. Control Register */
61+
62+
#define CPG_SD0CKCR1 0x8a4 /* SD-IF0 Clock Freq. Control Reg. 1 */
63+
64+
#define CPG_SD0CKCR1_SDSRC_SEL GENMASK(30, 29) /* SDSRC clock freq. select */
65+
5866
/* PLL Clocks */
5967
struct cpg_pll_clk {
6068
struct clk_hw hw;
@@ -392,15 +400,16 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
392400

393401
case CLK_TYPE_GEN4_PLL2X_3X:
394402
value = readl(base + core->offset);
395-
mult = (((value >> 24) & 0x7f) + 1) * 2;
403+
mult = (FIELD_GET(CPG_PLLxCR_STC, value) + 1) * 2;
396404
break;
397405

398406
case CLK_TYPE_GEN4_Z:
399407
return cpg_z_clk_register(core->name, __clk_get_name(parent),
400408
base, core->div, core->offset);
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402410
case CLK_TYPE_GEN4_SDSRC:
403-
div = ((readl(base + SD0CKCR1) >> 29) & 0x03) + 4;
411+
value = readl(base + CPG_SD0CKCR1);
412+
div = FIELD_GET(CPG_SD0CKCR1_SDSRC_SEL, value) + 4;
404413
break;
405414

406415
case CLK_TYPE_GEN4_SDH:

drivers/clk/renesas/rcar-gen4-cpg.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,6 @@ struct rcar_gen4_cpg_pll_config {
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u8 osc_prediv;
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};
6969

70-
#define CPG_RPCCKCR 0x874
71-
#define SD0CKCR1 0x8a4
72-
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struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,

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