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Merge tag 'samsung-dt64-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.10, part two Few changes exclusively for Google GS101: 1. Add HSI0 and HSI2 clock controllers (CMUs). 2. Add USB 3.1 Dual Role Device (DRD) support. 3. Add UFS (Universal Flash Storage) support. 4. Document bus clocks in pin controllers necessary for accessing registers. * tag 'samsung-dt64-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2 arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01] arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes arm64: dts: exynos: gs101: Add the hsi2 sysreg node dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible arm64: dts: exynos: gs101-oriole: enable USB on this board arm64: dts: exynos: gs101: add USB & USB-phy nodes arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎Documentation/devicetree/bindings/clock/google,gs101-clock.yaml‎

Lines changed: 53 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,16 +30,18 @@ properties:
3030
- google,gs101-cmu-top
3131
- google,gs101-cmu-apm
3232
- google,gs101-cmu-misc
33+
- google,gs101-cmu-hsi0
34+
- google,gs101-cmu-hsi2
3335
- google,gs101-cmu-peric0
3436
- google,gs101-cmu-peric1
3537

3638
clocks:
3739
minItems: 1
38-
maxItems: 3
40+
maxItems: 5
3941

4042
clock-names:
4143
minItems: 1
42-
maxItems: 3
44+
maxItems: 5
4345

4446
"#clock-cells":
4547
const: 1
@@ -72,6 +74,55 @@ allOf:
7274
items:
7375
- const: oscclk
7476

77+
- if:
78+
properties:
79+
compatible:
80+
contains:
81+
const: google,gs101-cmu-hsi0
82+
83+
then:
84+
properties:
85+
clocks:
86+
items:
87+
- description: External reference clock (24.576 MHz)
88+
- description: HSI0 bus clock (from CMU_TOP)
89+
- description: DPGTC (from CMU_TOP)
90+
- description: USB DRD controller clock (from CMU_TOP)
91+
- description: USB Display Port debug clock (from CMU_TOP)
92+
93+
clock-names:
94+
items:
95+
- const: oscclk
96+
- const: bus
97+
- const: dpgtc
98+
- const: usb31drd
99+
- const: usbdpdbg
100+
101+
- if:
102+
properties:
103+
compatible:
104+
contains:
105+
enum:
106+
- google,gs101-cmu-hsi2
107+
108+
then:
109+
properties:
110+
clocks:
111+
items:
112+
- description: External reference clock (24.576 MHz)
113+
- description: High Speed Interface bus clock (from CMU_TOP)
114+
- description: High Speed Interface pcie clock (from CMU_TOP)
115+
- description: High Speed Interface ufs clock (from CMU_TOP)
116+
- description: High Speed Interface mmc clock (from CMU_TOP)
117+
118+
clock-names:
119+
items:
120+
- const: oscclk
121+
- const: bus
122+
- const: pcie
123+
- const: ufs
124+
- const: mmc
125+
75126
- if:
76127
properties:
77128
compatible:

‎Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ properties:
1515
- items:
1616
- enum:
1717
- google,gs101-apm-sysreg
18+
- google,gs101-hsi2-sysreg
1819
- google,gs101-peric0-sysreg
1920
- google,gs101-peric1-sysreg
2021
- samsung,exynos3-sysreg
@@ -72,6 +73,7 @@ allOf:
7273
compatible:
7374
contains:
7475
enum:
76+
- google,gs101-hsi2-sysreg
7577
- google,gs101-peric0-sysreg
7678
- google,gs101-peric1-sysreg
7779
- samsung,exynos850-cmgp-sysreg

‎arch/arm64/boot/dts/exynos/google/gs101-oriole.dts‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,21 @@
5353
wakeup-source;
5454
};
5555
};
56+
57+
/* TODO: Remove this once PMIC is implemented */
58+
reg_placeholder: regulator-0 {
59+
compatible = "regulator-fixed";
60+
regulator-name = "placeholder_reg";
61+
};
62+
63+
/* TODO: Remove this once S2MPG11 slave PMIC is implemented */
64+
ufs_0_fixed_vcc_reg: regulator-1 {
65+
compatible = "regulator-fixed";
66+
regulator-name = "ufs-vcc";
67+
gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>;
68+
regulator-boot-on;
69+
enable-active-high;
70+
};
5671
};
5772

5873
&ext_24_5m {
@@ -106,6 +121,33 @@
106121
status = "okay";
107122
};
108123

124+
&ufs_0 {
125+
status = "okay";
126+
vcc-supply = <&ufs_0_fixed_vcc_reg>;
127+
};
128+
129+
&ufs_0_phy {
130+
status = "okay";
131+
};
132+
133+
&usbdrd31 {
134+
status = "okay";
135+
vdd10-supply = <&reg_placeholder>;
136+
vdd33-supply = <&reg_placeholder>;
137+
};
138+
139+
&usbdrd31_dwc3 {
140+
dr_mode = "otg";
141+
usb-role-switch;
142+
role-switch-default-mode = "peripheral";
143+
maximum-speed = "super-speed-plus";
144+
status = "okay";
145+
};
146+
147+
&usbdrd31_phy {
148+
status = "okay";
149+
};
150+
109151
&usi_uart {
110152
samsung,clkreq-on; /* needed for UART mode */
111153
status = "okay";

‎arch/arm64/boot/dts/exynos/google/gs101.dtsi‎

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -370,6 +370,8 @@
370370
pinctrl_peric0: pinctrl@10840000 {
371371
compatible = "google,gs101-pinctrl";
372372
reg = <0x10840000 0x00001000>;
373+
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>;
374+
clock-names = "pclk";
373375
interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
374376
};
375377

@@ -914,6 +916,8 @@
914916
pinctrl_peric1: pinctrl@10c40000 {
915917
compatible = "google,gs101-pinctrl";
916918
reg = <0x10c40000 0x00001000>;
919+
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>;
920+
clock-names = "pclk";
917921
interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
918922
};
919923

@@ -1247,18 +1251,132 @@
12471251
};
12481252
};
12491253

1254+
cmu_hsi0: clock-controller@11000000 {
1255+
compatible = "google,gs101-cmu-hsi0";
1256+
reg = <0x11000000 0x4000>;
1257+
#clock-cells = <1>;
1258+
1259+
clocks = <&ext_24_5m>,
1260+
<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
1261+
<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>,
1262+
<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
1263+
<&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>;
1264+
clock-names = "oscclk", "bus", "dpgtc", "usb31drd",
1265+
"usbdpdbg";
1266+
};
1267+
1268+
usbdrd31_phy: phy@11100000 {
1269+
compatible = "google,gs101-usb31drd-phy";
1270+
reg = <0x11100000 0x0100>,
1271+
<0x110f0000 0x0800>,
1272+
<0x110e0000 0x2800>;
1273+
reg-names = "phy", "pcs", "pma";
1274+
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>,
1275+
<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>,
1276+
<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>,
1277+
<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>,
1278+
<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>;
1279+
clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk";
1280+
samsung,pmu-syscon = <&pmu_system_controller>;
1281+
#phy-cells = <1>;
1282+
status = "disabled";
1283+
};
1284+
1285+
usbdrd31: usb@11110000 {
1286+
compatible = "google,gs101-dwusb3";
1287+
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>,
1288+
<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>,
1289+
<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>,
1290+
<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>;
1291+
clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk";
1292+
#address-cells = <1>;
1293+
#size-cells = <1>;
1294+
ranges = <0x0 0x11110000 0x10000>;
1295+
status = "disabled";
1296+
1297+
usbdrd31_dwc3: usb@0 {
1298+
compatible = "snps,dwc3";
1299+
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>;
1300+
clock-names = "ref";
1301+
reg = <0x0 0x10000>;
1302+
interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
1303+
phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>;
1304+
phy-names = "usb2-phy", "usb3-phy";
1305+
status = "disabled";
1306+
};
1307+
};
1308+
12501309
pinctrl_hsi1: pinctrl@11840000 {
12511310
compatible = "google,gs101-pinctrl";
12521311
reg = <0x11840000 0x00001000>;
1312+
/* TODO: update once support for this CMU exists */
1313+
clocks = <0>;
1314+
clock-names = "pclk";
12531315
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
12541316
};
12551317

1318+
cmu_hsi2: clock-controller@14400000 {
1319+
compatible = "google,gs101-cmu-hsi2";
1320+
reg = <0x14400000 0x4000>;
1321+
#clock-cells = <1>;
1322+
clocks = <&ext_24_5m>,
1323+
<&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
1324+
<&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
1325+
<&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
1326+
<&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
1327+
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
1328+
};
1329+
1330+
sysreg_hsi2: syscon@14420000 {
1331+
compatible = "google,gs101-hsi2-sysreg", "syscon";
1332+
reg = <0x14420000 0x10000>;
1333+
clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
1334+
};
1335+
12561336
pinctrl_hsi2: pinctrl@14440000 {
12571337
compatible = "google,gs101-pinctrl";
12581338
reg = <0x14440000 0x00001000>;
1339+
clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>;
1340+
clock-names = "pclk";
12591341
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
12601342
};
12611343

1344+
ufs_0: ufs@14700000 {
1345+
compatible = "google,gs101-ufs";
1346+
reg = <0x14700000 0x200>,
1347+
<0x14701100 0x200>,
1348+
<0x14780000 0xa000>,
1349+
<0x14600000 0x100>;
1350+
reg-names = "hci", "vs_hci", "unipro", "ufsp";
1351+
interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
1352+
clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
1353+
<&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
1354+
<&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
1355+
<&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
1356+
<&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>,
1357+
<&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
1358+
clock-names = "core_clk", "sclk_unipro_main", "fmp",
1359+
"aclk", "pclk", "sysreg";
1360+
freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
1361+
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
1362+
pinctrl-names = "default";
1363+
phys = <&ufs_0_phy>;
1364+
phy-names = "ufs-phy";
1365+
samsung,sysreg = <&sysreg_hsi2 0x710>;
1366+
status = "disabled";
1367+
};
1368+
1369+
ufs_0_phy: phy@14704000 {
1370+
compatible = "google,gs101-ufs-phy";
1371+
reg = <0x14704000 0x3000>;
1372+
reg-names = "phy-pma";
1373+
samsung,pmu-syscon = <&pmu_system_controller>;
1374+
#phy-cells = <0>;
1375+
clocks = <&ext_24_5m>;
1376+
clock-names = "ref_clk";
1377+
status = "disabled";
1378+
};
1379+
12621380
cmu_apm: clock-controller@17400000 {
12631381
compatible = "google,gs101-cmu-apm";
12641382
reg = <0x17400000 0x8000>;
@@ -1281,6 +1399,8 @@
12811399
pinctrl_gpio_alive: pinctrl@174d0000 {
12821400
compatible = "google,gs101-pinctrl";
12831401
reg = <0x174d0000 0x00001000>;
1402+
clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>;
1403+
clock-names = "pclk";
12841404

12851405
wakeup-interrupt-controller {
12861406
compatible = "google,gs101-wakeup-eint",
@@ -1292,6 +1412,8 @@
12921412
pinctrl_far_alive: pinctrl@174e0000 {
12931413
compatible = "google,gs101-pinctrl";
12941414
reg = <0x174e0000 0x00001000>;
1415+
clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>;
1416+
clock-names = "pclk";
12951417

12961418
wakeup-interrupt-controller {
12971419
compatible = "google,gs101-wakeup-eint",
@@ -1303,11 +1425,17 @@
13031425
pinctrl_gsactrl: pinctrl@17940000 {
13041426
compatible = "google,gs101-pinctrl";
13051427
reg = <0x17940000 0x00001000>;
1428+
/* TODO: update once support for this CMU exists */
1429+
clocks = <0>;
1430+
clock-names = "pclk";
13061431
};
13071432

13081433
pinctrl_gsacore: pinctrl@17a80000 {
13091434
compatible = "google,gs101-pinctrl";
13101435
reg = <0x17a80000 0x00001000>;
1436+
/* TODO: update once support for this CMU exists */
1437+
clocks = <0>;
1438+
clock-names = "pclk";
13111439
};
13121440

13131441
cmu_top: clock-controller@1e080000 {

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