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# Justfile for Conv2D testbench
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# Common Verilator flags
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VFLAGS := "--binary --timing"
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VFLAGS_TRACE := "--binary --timing --trace"
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VFLAGS_LINT := "-Wall --lint-only"
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SOURCES := "conv2d_tb.sv valid-hold.sv"
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# Default target
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default: build
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# Build the testbench with Verilator
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build:
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verilator {{VFLAGS}} -o sim {{SOURCES}}
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# Build with VCD tracing support
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build-trace:
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verilator {{VFLAGS_TRACE}} -o sim {{SOURCES}}
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# Lint the files
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lint:
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verilator {{VFLAGS_LINT}} {{SOURCES}}
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# Run the simulation
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run: build
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./obj_dir/sim
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# Run with VCD tracing
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run-trace: build-trace
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./obj_dir/sim
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# Clean build artifacts
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clean:
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rm -rf obj_dir *.vcd tests/*_n*.sv tests/*_d*_n*.sv
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# Test with different N values (with VCD tracing)
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# Test a specific N value with custom name
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test-n N:
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sed 's/parameter N = 4;/parameter N = {{N}};/' tests/conv2d_tb.sv > tests/conv2d_tb_n{{N}}.sv
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verilator {{VFLAGS_TRACE}} -o sim_n{{N}} tests/conv2d_tb_n{{N}}.sv valid-hold.sv
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./obj_dir/sim_n{{N}}
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@[ -f conv2d_tb.vcd ] && mv conv2d_tb.vcd conv2d_tb_n{{N}}.vcd || true
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rm tests/conv2d_tb_n{{N}}.sv
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# Test Blur module with specific D and N values
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test-blur D N:
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@echo "Testing Blur with D={{D}}, N={{N}}"
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@if [ {{D}} -lt 4 ]; then echo "Error: D must be >= 4"; exit 1; fi
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sed 's/parameter D = 8;/parameter D = {{D}};/' tests/blur_tb.sv > tests/blur_tb_d{{D}}_n{{N}}.sv
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sed -i '' 's/parameter N = 4;/parameter N = {{N}};/' tests/blur_tb_d{{D}}_n{{N}}.sv
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verilator {{VFLAGS_TRACE}} -o sim_blur_d{{D}}_n{{N}} tests/blur_tb_d{{D}}_n{{N}}.sv valid-hold.sv
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./obj_dir/sim_blur_d{{D}}_n{{N}}
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@[ -f blur_tb.vcd ] && mv blur_tb.vcd blur_tb_d{{D}}_n{{N}}.vcd || true
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rm tests/blur_tb_d{{D}}_n{{N}}.sv
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# Quick blur test with default parameters
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test-blur-default: (test-blur "8" "4")
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File renamed without changes.
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`timescale 1ns/1ps
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module Conv2D_tb;
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// Clock and reset
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logic clk;
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logic reset;
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// Test parameters
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parameter N = 16; // Can be 1, 2, 4, 8, or 16
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// DUT signals
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logic valid_i;
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logic ready_i;
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logic[15:0][7:0] data_in;
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logic valid_o;
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logic ready_o;
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logic[15:0][7:0] data_out;
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int cycles, start_v, end_v;
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// Verification variables
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logic pass;
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logic[7:0] expected;
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// Instantiate DUT
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Conv2D #(.N(N)) dut (
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.clk(clk),
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.reset(reset),
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.valid_i(valid_i),
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.ready_i(ready_i),
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.i(data_in),
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.valid_o(valid_o),
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.ready_o(ready_o),
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.o(data_out)
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);
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// Clock generation
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initial begin
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clk = 0;
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forever #5 clk = ~clk; // 100MHz clock
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end
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// Dump waveforms
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initial begin
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$dumpfile("conv2d_tb.vcd");
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$dumpvars(0, Conv2D_tb);
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end
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always_ff @(posedge clk) begin
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if (reset) cycles <= '0;
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else cycles <= cycles + 1;
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if (cycles > 50) begin
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$display("timeout at 100 cycles!");
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$finish;
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end
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if (valid_i) start_v <= cycles;
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if (valid_o) end_v <= cycles;
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end
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// Test stimulus
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initial begin
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// Initialize signals
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reset = 1;
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valid_i = 0;
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ready_o = 0;
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data_in = '0;
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// Hold reset for 5 cycles
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repeat(5) @(posedge clk);
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reset = 0;
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@(posedge clk);
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// Prepare input data [0..15]
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for (int i = 0; i < 16; i++) begin
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data_in[i] = i[7:0];
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end
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$display("Starting test with N=%0d", N);
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$display("Input data: ");
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for (int i = 0; i < 16; i++) begin
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$write("%3d ", data_in[i]);
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if ((i+1) % 4 == 0) $write("\n");
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end
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// Wait for module to be ready
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@(posedge clk);
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while (!ready_i) begin
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@(posedge clk);
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end
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// Send input data
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$display("\nSending data to Conv2D module...");
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valid_i = 1;
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@(posedge clk);
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// Check if transaction occurred
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if (ready_i && valid_i) begin
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$display("Transaction accepted by module");
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end
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valid_i = 0; // Clear valid after one cycle
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// Wait for output to be valid
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$display("Waiting for output...");
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while (!valid_o) begin
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@(posedge clk);
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end
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// Assert ready to accept output
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ready_o = 1;
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@(posedge clk);
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// Print output
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$display("\nOutput data received:");
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for (int i = 0; i < 16; i++) begin
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$write("%3d ", data_out[i]);
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if ((i+1) % 4 == 0) $write("\n");
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end
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// Verify output (should be input + 2)
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$display("\nVerifying output (each element should be input + 2):");
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pass = 1;
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for (int i = 0; i < 16; i++) begin
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expected = i[7:0] + 2;
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if (data_out[i] !== expected) begin
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$display("ERROR: data_out[%2d] = %3d, expected %3d", i, data_out[i], expected);
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pass = 0;
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end
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end
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if (pass) begin
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$display("PASS: All outputs are correct!");
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end else begin
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$display("FAIL: Output mismatch detected!");
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end
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ready_o = 0;
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// Wait a few cycles then end
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repeat(10) @(posedge clk);
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$display("\nTest completed! Latency: %0d, Cycles: %0d", end_v-start_v, cycles);
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$finish;
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end
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endmodule

apps/guass-pyramid/ready-val/valid-hold.sv

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,8 @@ module Conv2D#(
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// Interface with the convolution module
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logic conv_valid_i, conv_valid_o;
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logic[N-1:0][7:0] conv_out, conv_in;
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logic[N-1:0][7:0] conv_out;
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logic[N-1:0][7:0] conv_in;
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AetherlingConv#(.N(N)) Conv(
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.clk, .reset,
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.in(conv_in),
@@ -328,7 +329,7 @@ module Blur#(
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// Should apply blur kernel to each pixel neighborhood and manage ready/valid protocol
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logic conv_ready_i, conv_ready_o, conv_valid_i, conv_valid_o;
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logic[15:0][7:0] conv_in, conv_out;
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logic[N-1:0][7:0] conv_in, conv_out;
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Conv2D#(.N(N)) conv2d(
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.clk, .reset,

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