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| 1 | +`timescale 1ns/1ps |
| 2 | + |
| 3 | +module Conv2D_tb; |
| 4 | + |
| 5 | +// Clock and reset |
| 6 | +logic clk; |
| 7 | +logic reset; |
| 8 | + |
| 9 | +// Test parameters |
| 10 | +parameter N = 16; // Can be 1, 2, 4, 8, or 16 |
| 11 | + |
| 12 | +// DUT signals |
| 13 | +logic valid_i; |
| 14 | +logic ready_i; |
| 15 | +logic[15:0][7:0] data_in; |
| 16 | +logic valid_o; |
| 17 | +logic ready_o; |
| 18 | +logic[15:0][7:0] data_out; |
| 19 | +int cycles, start_v, end_v; |
| 20 | + |
| 21 | +// Verification variables |
| 22 | +logic pass; |
| 23 | +logic[7:0] expected; |
| 24 | + |
| 25 | +// Instantiate DUT |
| 26 | +Conv2D #(.N(N)) dut ( |
| 27 | + .clk(clk), |
| 28 | + .reset(reset), |
| 29 | + .valid_i(valid_i), |
| 30 | + .ready_i(ready_i), |
| 31 | + .i(data_in), |
| 32 | + .valid_o(valid_o), |
| 33 | + .ready_o(ready_o), |
| 34 | + .o(data_out) |
| 35 | +); |
| 36 | + |
| 37 | +// Clock generation |
| 38 | +initial begin |
| 39 | + clk = 0; |
| 40 | + forever #5 clk = ~clk; // 100MHz clock |
| 41 | +end |
| 42 | + |
| 43 | +// Dump waveforms |
| 44 | +initial begin |
| 45 | + $dumpfile("conv2d_tb.vcd"); |
| 46 | + $dumpvars(0, Conv2D_tb); |
| 47 | +end |
| 48 | + |
| 49 | +always_ff @(posedge clk) begin |
| 50 | + if (reset) cycles <= '0; |
| 51 | + else cycles <= cycles + 1; |
| 52 | + |
| 53 | + if (cycles > 50) begin |
| 54 | + $display("timeout at 100 cycles!"); |
| 55 | + $finish; |
| 56 | + end |
| 57 | + |
| 58 | + if (valid_i) start_v <= cycles; |
| 59 | + if (valid_o) end_v <= cycles; |
| 60 | +end |
| 61 | + |
| 62 | +// Test stimulus |
| 63 | +initial begin |
| 64 | + // Initialize signals |
| 65 | + reset = 1; |
| 66 | + valid_i = 0; |
| 67 | + ready_o = 0; |
| 68 | + data_in = '0; |
| 69 | + |
| 70 | + // Hold reset for 5 cycles |
| 71 | + repeat(5) @(posedge clk); |
| 72 | + reset = 0; |
| 73 | + @(posedge clk); |
| 74 | + |
| 75 | + // Prepare input data [0..15] |
| 76 | + for (int i = 0; i < 16; i++) begin |
| 77 | + data_in[i] = i[7:0]; |
| 78 | + end |
| 79 | + |
| 80 | + $display("Starting test with N=%0d", N); |
| 81 | + $display("Input data: "); |
| 82 | + for (int i = 0; i < 16; i++) begin |
| 83 | + $write("%3d ", data_in[i]); |
| 84 | + if ((i+1) % 4 == 0) $write("\n"); |
| 85 | + end |
| 86 | + |
| 87 | + // Wait for module to be ready |
| 88 | + @(posedge clk); |
| 89 | + while (!ready_i) begin |
| 90 | + @(posedge clk); |
| 91 | + end |
| 92 | + |
| 93 | + // Send input data |
| 94 | + $display("\nSending data to Conv2D module..."); |
| 95 | + valid_i = 1; |
| 96 | + @(posedge clk); |
| 97 | + |
| 98 | + // Check if transaction occurred |
| 99 | + if (ready_i && valid_i) begin |
| 100 | + $display("Transaction accepted by module"); |
| 101 | + end |
| 102 | + |
| 103 | + valid_i = 0; // Clear valid after one cycle |
| 104 | + |
| 105 | + // Wait for output to be valid |
| 106 | + $display("Waiting for output..."); |
| 107 | + while (!valid_o) begin |
| 108 | + @(posedge clk); |
| 109 | + end |
| 110 | + |
| 111 | + // Assert ready to accept output |
| 112 | + ready_o = 1; |
| 113 | + @(posedge clk); |
| 114 | + |
| 115 | + // Print output |
| 116 | + $display("\nOutput data received:"); |
| 117 | + for (int i = 0; i < 16; i++) begin |
| 118 | + $write("%3d ", data_out[i]); |
| 119 | + if ((i+1) % 4 == 0) $write("\n"); |
| 120 | + end |
| 121 | + |
| 122 | + // Verify output (should be input + 2) |
| 123 | + $display("\nVerifying output (each element should be input + 2):"); |
| 124 | + pass = 1; |
| 125 | + for (int i = 0; i < 16; i++) begin |
| 126 | + expected = i[7:0] + 2; |
| 127 | + if (data_out[i] !== expected) begin |
| 128 | + $display("ERROR: data_out[%2d] = %3d, expected %3d", i, data_out[i], expected); |
| 129 | + pass = 0; |
| 130 | + end |
| 131 | + end |
| 132 | + |
| 133 | + if (pass) begin |
| 134 | + $display("PASS: All outputs are correct!"); |
| 135 | + end else begin |
| 136 | + $display("FAIL: Output mismatch detected!"); |
| 137 | + end |
| 138 | + |
| 139 | + ready_o = 0; |
| 140 | + |
| 141 | + // Wait a few cycles then end |
| 142 | + repeat(10) @(posedge clk); |
| 143 | + |
| 144 | + $display("\nTest completed! Latency: %0d, Cycles: %0d", end_v-start_v, cycles); |
| 145 | + $finish; |
| 146 | +end |
| 147 | + |
| 148 | +endmodule |
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