aetherling interface change

Author: rachitnigam

apps/aetherling/common/fast-interface.fil

@@ -27,10 +27,11 @@ comp Conv2dAbstract<'G: 1>(
 /// 16 inputs at the same time and exactly for one cycle.
 comp Wrapper<'G: II>(
     valid_up: interface['G],
-    I[16]: ['G, 'G+1] 8
+    I[16]: ['G, 'G+H] 8
 ) -> (
     O[16]: ['G+L, 'G+L+1] 8
 ) with {
+    some H where H == 1;
     /// The latency of the module
     some L where L > 0;
     /// The initiation interval of the module
@@ -72,6 +73,8 @@ comp Wrapper<'G: II>(
 
     // The II is limited by the speed at which the convolution can process the inputs.
     II := 16/C::N;
+
+    H := 1;
 }
 
 // The main component has the same interface for each design
@@ -134,4 +137,4 @@ comp main<'G: II>(
 
     L := W::L;
     II := W::II;
-}
+}

apps/aetherling/common/slow-interface.fil

@@ -132,4 +132,4 @@ comp main<'G: II>(
     L := W::L;
     II := W::II;
     H := W::H;
-}
+}

primitives/param-funcs.fil

@@ -12,3 +12,17 @@ comp BitsNeeded[N]<'G:1>() -> () with {
   let Bits = log2(N)+1; assume Bits > 0;
   Out := Bits;
 }
+
+/// Return the parameter that is the maximum of A or B.
+comp Max[A, B]<'G:1>() -> () with {
+  some Out where Out == if A > B { A } else { B };
+} {
+  Out := if A > B { A } else { B };
+}
+
+/// Return the parameter that is the minimum of A or B.
+comp Min[A, B]<'G:1>() -> () with {
+  some Out where Out == if A > B { B } else { A };
+} {
+  Out := if A > B { B } else { A };
+}

primitives/reshape.fil

@@ -103,6 +103,7 @@ comp Deserialize[W, N, B, ?C=1, ?H=1]<'G: End-1>(
     }
 }
 
+
 /// Take a bundle of length L that produces values every N and cycles and make
 /// it produce values every M cycles where M > N.
 comp Downsample[N, M, L, W]<'G: (M-N)*L>(

primitives/state.fil

@@ -77,6 +77,36 @@ comp Shift[W, D, ?N=1]<'G: 1>(
 }
 /* ANCHOR_END: shift */
 
+/// Shift 2D bundle of signals
+comp Shift2D[W, D0, D1, ?N=1]<'G:1>(
+  in[D0][D1]: ['G, 'G+1] W
+) -> (
+  out[D0][D1]: ['G+N, 'G+N+1] W
+) where W > 0, D0 > 0, D1 > 0, N > 0 {
+  for i in 0..D0 {
+    for j in 0..D1 {
+      s := new Shift[W, N]<'G>(in{i}{j});
+      out{i}{j} = s.out;
+    }
+  }
+}
+
+/// Hold 2D bundle of signals active for multiple cycles.
+comp Strech2D[W, D0, D1, H]<'G:H>(
+  en: interface['G],
+  in[D0][D1]: ['G, 'G+1] W
+) -> (
+  out[D0][D1]: ['G+1, 'G+H+1] W
+) where W > 0, D0 > 0, D1 > 0, H > 0 {
+  for i in 0..D0 {
+    for j in 0..D1 {
+      r := new Register[W]<'G, 'G+H+1>(in{i}{j});
+      out{i}{j} = r.out;
+    }
+  }
+}
+
+
 // A counter that counts up by one every time `en` is asserted and resets
 // when it reaches the value `N`.
 comp Counter[W, N]<'G:1>(