working conv2d

Author: rachitnigam

apps/guass-pyramid/ready-val/conv2d_tb.sv

@@ -0,0 +1,148 @@
+`timescale 1ns/1ps
+
+module Conv2D_tb;
+
+// Clock and reset
+logic clk;
+logic reset;
+
+// Test parameters
+parameter N = 4;  // Can be 1, 2, 4, 8, or 16
+
+// DUT signals
+logic valid_i;
+logic ready_i;
+logic[15:0][7:0] data_in;
+logic valid_o;
+logic ready_o;
+logic[15:0][7:0] data_out;
+int cycles, start_v, end_v;
+
+// Verification variables
+logic pass;
+logic[7:0] expected;
+
+// Instantiate DUT
+Conv2D #(.N(N)) dut (
+  .clk(clk),
+  .reset(reset),
+  .valid_i(valid_i),
+  .ready_i(ready_i),
+  .i(data_in),
+  .valid_o(valid_o),
+  .ready_o(ready_o),
+  .o(data_out)
+);
+
+// Clock generation
+initial begin
+  clk = 0;
+  forever #5 clk = ~clk;  // 100MHz clock
+end
+
+// Dump waveforms
+initial begin
+  $dumpfile("conv2d_tb.vcd");
+  $dumpvars(0, Conv2D_tb);
+end
+
+always_ff @(posedge clk) begin
+  if (reset) cycles <= '0;
+  else cycles <= cycles + 1;
+
+  if (cycles > 50) begin
+    $display("timeout at 100 cycles!");
+    $finish;
+  end
+
+  if (valid_i) start_v <= cycles;
+  if (valid_o) end_v <= cycles;
+end
+
+// Test stimulus
+initial begin
+  // Initialize signals
+  reset = 1;
+  valid_i = 0;
+  ready_o = 0;
+  data_in = '0;
+
+  // Hold reset for 5 cycles
+  repeat(5) @(posedge clk);
+  reset = 0;
+  @(posedge clk);
+
+  // Prepare input data [0..15]
+  for (int i = 0; i < 16; i++) begin
+    data_in[i] = i[7:0];
+  end
+
+  $display("Starting test with N=%0d", N);
+  $display("Input data: ");
+  for (int i = 0; i < 16; i++) begin
+    $write("%3d ", data_in[i]);
+    if ((i+1) % 4 == 0) $write("\n");
+  end
+
+  // Wait for module to be ready
+  @(posedge clk);
+  while (!ready_i) begin
+    @(posedge clk);
+  end
+
+  // Send input data
+  $display("\nSending data to Conv2D module...");
+  valid_i = 1;
+  @(posedge clk);
+
+  // Check if transaction occurred
+  if (ready_i && valid_i) begin
+    $display("Transaction accepted by module");
+  end
+
+  valid_i = 0;  // Clear valid after one cycle
+
+  // Wait for output to be valid
+  $display("Waiting for output...");
+  while (!valid_o) begin
+    @(posedge clk);
+  end
+
+  // Assert ready to accept output
+  ready_o = 1;
+  @(posedge clk);
+
+  // Print output
+  $display("\nOutput data received:");
+  for (int i = 0; i < 16; i++) begin
+    $write("%3d ", data_out[i]);
+    if ((i+1) % 4 == 0) $write("\n");
+  end
+
+  // Verify output (should be input + 2)
+  $display("\nVerifying output (each element should be input + 2):");
+  pass = 1;
+  for (int i = 0; i < 16; i++) begin
+    expected = i[7:0] + 2;
+    if (data_out[i] !== expected) begin
+      $display("ERROR: data_out[%2d] = %3d, expected %3d", i, data_out[i], expected);
+      pass = 0;
+    end
+  end
+
+  if (pass) begin
+    $display("PASS: All outputs are correct!");
+  end else begin
+    $display("FAIL: Output mismatch detected!");
+  end
+
+  ready_o = 0;
+
+  // Wait a few cycles then end
+  repeat(10) @(posedge clk);
+
+  $display("\nTest completed! Latency: %0d, Cycles: %0d", end_v-start_v, cycles);
+  $finish;
+end
+
+endmodule

apps/guass-pyramid/ready-val/valid-hold.sv

@@ -126,7 +126,7 @@ module Conv2D#(
 // Interface with the convolution module
 logic conv_valid_i, conv_valid_o;
 logic[N-1:0][7:0] conv_out, conv_in;
-AetherlingConv#(.N) Conv(
+AetherlingConv#(.N(N)) Conv(
   .clk, .reset,
   .in(conv_in),
   .valid_i(conv_valid_i),
@@ -148,14 +148,14 @@ end
 
 // The chunk we are working on.
 localparam Chunks = 16 / N;
+localparam Chunks_1 = Chunks - 1;
 logic[3:0] idx, nxt_idx;
 always_ff @(posedge clk) begin
   if (reset) idx <= '0;
   else idx <= nxt_idx;
 end
 
-wire last_chunk = idx == Chunks[3:0]-1;
-
+wire last_chunk = idx == Chunks_1[3:0];
 
 // State machine
 logic[1:0] st, nxt_st;
@@ -170,14 +170,19 @@ always_comb begin
     end
     PROC_SEND: begin
       nxt_st = PROC_RECV;
-      nxt_idx = idx + 1;
       conv_valid_i = 1;
     end
     PROC_RECV: begin
       // If the convolution module has returned a valid value.
       if (conv_valid_o) begin
-        if (last_chunk) nxt_st = WRITING; // This is the last chunk. Finish processing.
-        else nxt_st = PROC_SEND;          // More chunks remain.
+        // This is the last chunk. Finish processing.
+        if (last_chunk) begin
+          nxt_idx = '0;
+          nxt_st = WRITING;
+        end else begin
+          nxt_idx = idx + 1;
+          nxt_st = PROC_SEND;
+        end
       end
     end
     WRITING: begin
@@ -195,7 +200,7 @@ always_comb begin
   conv_in = '0;
   for (int j = 0; j < Chunks; j++) begin
     if (idx == j[3:0]) begin
-      conv_in = in[(N*(j+1)-1)+:N];
+      conv_in = in[N*j+:N];
     end
   end
 end
@@ -206,15 +211,82 @@ always_comb begin
   for (int j = 0; j < Chunks; j++) begin
     // If the output is valid;
     if (conv_valid_o && idx == j[3:0]) begin
-      out[(N*(j+1)-1)+:N] = conv_out;
+      // $display("writing to chunk %0d: [%0d:%0d]", j[3:0], N*j+N, N*j);
+      out[N*j+:N] = conv_out;
     end
   end
 end
 always_ff @(posedge clk) begin
   o <= out;
+  /*
+  if (conv_valid_o) begin
+    $write("out: ");
+    for (int i = 0; i < 16; i++)
+      $write("%0d,", out[i]);
+    $write("; conv_out: ");
+    for (int i = 0; i < N; i++)
+      $write("%0d,", conv_out[i]);
+    $display("");
+  end
+  */
 end
 
 assign valid_o = st == WRITING;
 assign ready_i = st == IDLE;
 
 endmodule
+
+// Pad the input image by a row and a column;
+module Pad#(
+  parameter D0 = 8,
+  parameter D1 = 8,
+  parameter W = 8
+) (
+  input logic[D0-1:0][D1-1:0][W-1:0] in,
+  output logic[D0+1:0][D1+1:0][W-1:0] out
+);
+
+always_comb begin
+  out = '0;
+  // Copy input to the center of the output array
+  for (int i = 0; i < D0; i++) begin
+    for (int j = 0; j < D1; j++) begin
+      out[i+1][j+1] = in[i][j];
+    end
+  end
+end
+
+endmodule
+
+// Downsample by taking every other row and column
+module Downsample#(
+  parameter D0 = 8,
+  parameter D1 = 8,
+  parameter W = 8
+) (
+  input logic[D0-1:0][D1-1:0][W-1:0] in,
+  output logic[D0/2-1:0][D1/2-1:0][W-1:0] out
+);
+always_comb begin
+  for (int i = 0; i < D0/2; i++) begin
+    for (int j = 0; j < D1/2; j++) begin
+      out[i][j] = in[2*i][2*j];
+    end
+  end
+end
+endmodule
+
+module Pyramid (
+  input logic clk,
+  input logic reset,
+
+  input logic valid_i,
+  output logic ready_i,
+  input logic[15:0][7:0] in,
+
+  output logic valid_o,
+  input logic ready_o,
+  output logic[15:0][7:0] out
+);
+
+endmodule