@@ -523,10 +523,16 @@ module Pyramid (
523523 input logic ready_o,
524524 output logic [7 : 0 ][7 : 0 ][7 : 0 ] out, // 8x8 output image
525525
526- // Debug signals
526+ // / Debug signals
527+ // Blur states
527528 output logic [1 : 0 ] blur0_st,
528529 output logic [1 : 0 ] blur1_st,
529- output logic [1 : 0 ] blur_up_st
530+ output logic [1 : 0 ] blur_up_st,
531+
532+ // Latched outputs
533+ output logic [7 : 0 ][7 : 0 ][7 : 0 ] level0_stable,
534+ output logic [3 : 0 ][3 : 0 ][7 : 0 ] level1_stable,
535+ output logic [7 : 0 ][7 : 0 ][7 : 0 ] upsampled_stable
530536);
531537
532538// Main state machine
@@ -625,7 +631,6 @@ Blur#(.D0(10), .D1(10)) blur0(
625631
626632// Store the image produced by the first level once valid is asserted
627633// in the right state.
628- logic [7 : 0 ][7 : 0 ][7 : 0 ] level0_stable;
629634always_ff @ (posedge clk) begin
630635 if (reset)
631636 level0_stable <= '0 ;
@@ -661,14 +666,13 @@ Blur#(.D0(6), .D1(6)) blur1(
661666 .out (blur1_out), .valid_o (blur1_valid_o), .ready_o (blur1_ready_o)
662667);
663668
664- logic [3 : 0 ][3 : 0 ][7 : 0 ] level1_out_stable;
665669always_ff @ (posedge clk) begin
666670 if (reset)
667- level1_out_stable <= '0 ;
671+ level1_stable <= '0 ;
668672 else if (st == Level1_Recv && blur1_valid_o)
669- level1_out_stable <= blur1_out;
673+ level1_stable <= blur1_out;
670674 else
671- level1_out_stable <= level1_out_stable ;
675+ level1_stable <= level1_stable ;
672676end
673677
674678// 3. UPSAMPLE PATH (blur.fil lines 341-351):
679683
680684logic [7 : 0 ][7 : 0 ][7 : 0 ] upsample_out;
681685Upsample # (.W (8 ), .D0 (4 ), .D1 (4 )) upsample (
682- .in (level1_out_stable ), .out (upsample_out)
686+ .in (level1_stable ), .out (upsample_out)
683687);
684688
685689logic [9 : 0 ][9 : 0 ][7 : 0 ] pad_up_out;
@@ -694,7 +698,6 @@ Blur#(.D0(10), .D1(10)) blur_up(
694698 .in (pad_up_out), .valid_i (blur_up_valid_i), .ready_i (blur_up_ready_i),
695699 .out (blur_up_out), .valid_o (blur_up_valid_o), .ready_o (blur_up_ready_o)
696700);
697- logic [7 : 0 ][7 : 0 ][7 : 0 ] upsampled_stable;
698701always_ff @ (posedge clk) begin
699702 if (reset)
700703 upsampled_stable <= '0 ;
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