[AMD][Raphael] Attempt to read the SoC voltage

Author: cyring

x86_64/amd_reg.h

@@ -2314,6 +2314,10 @@ typedef union
 	#define SMU_AMD_RMB_SVI(_plane) 	(0x0006f010 + (_plane << 2))
 #endif
 
+#ifndef SMU_AMD_F19H_SVI
+	#define SMU_AMD_F19H_SVI(_plane)	(0x0007300c + (_plane << 2))
+#endif
+
 typedef union
 {/*		--- SMU SVI [ 0x5a00c ; 0x5a010 ; 0x5a014 ; 0x6f038] ---
  *				[ CPU addr]	[ SoC addr]
@@ -2333,7 +2337,7 @@ typedef union
 		VID		: 24-16, /* Voltage: SVI{0,1}_PLANE0_VDDCOR */
 		ReservedBits2	: 32-24;
 	};
-} AMD_17_SVI;
+} AMD_F17H_SVI;
 
 typedef union
 {/*				--- SMU SVI [ Rembrandt ] ---
@@ -2369,13 +2373,16 @@ typedef union
 		ReservedBits	: 24-0, 	/*	MTS: All zeros	*/
 		VID		: 32-24;	/*	Voltage ID	*/
 	};
-} AMD_17_CORE_VID;
+} AMD_F17H_CORE_VID;
 
 typedef union
-{/*				--- SMU SVI [ Genoa ] ---
- * ZEN4 [AF_11] 		[ 0x5a010 ]	[ 0x5a014 ]
+{/*				--- SMU SVI [ ZEN4 ] ---
+ * Genoa [AF_11] 		[ 0x5a010 ]	[ 0x5a014 ]
  *			Idle:	0x00009a81	0x00019a81
  *			Load:	0x0000a401	0x0001a401
+ * Raphael [AF_61]		[ 0x73010 ]	[ 0x73014 ]
+ *			Idle:	0x0000bd41	0x0001bd41
+ *			Load:	0x0000b9c1	0x0001b901
  */
 	unsigned int		value;
 	struct {
@@ -2385,4 +2392,4 @@ typedef union
 		PKG		: 17-16,  /* 1 for 2nd processor socket */
 		RSVD		: 32-17;
 	};
-} AMD_GNA_SVI;
+} AMD_F19H_SVI;

x86_64/corefreqk.c

@@ -20521,7 +20521,7 @@ static void Call_Genoa_ACCU(CORE_RO *Core)
 	Call_HSMP_ACCU(Core);
 }
 
-static void SoC_RAPL(AMD_17_SVI SVI, const unsigned long long factor)
+static void SoC_RAPL(AMD_F17H_SVI SVI, const unsigned long long factor)
 {
 	unsigned long long VCC, ICC, ACCU;
 	/*	PLATFORM RAPL workaround to provide the SoC power	*/
@@ -20537,7 +20537,7 @@ static void SoC_RAPL(AMD_17_SVI SVI, const unsigned long long factor)
 static void Call_SVI(	const unsigned int plane0, const unsigned int plane1,
 			const unsigned long long factor )
 {
-	AMD_17_SVI SVI = {.value = 0};
+	AMD_F17H_SVI SVI = {.value = 0};
 
 	Core_AMD_SMN_Read(	SVI,
 				SMU_AMD_F17H_SVI(plane0),
@@ -20557,7 +20557,7 @@ static void Call_SVI(	const unsigned int plane0, const unsigned int plane1,
 static void Call_SVI_APU(const unsigned int plane0, const unsigned int plane1,
 			const unsigned long long factor)
 {
-	AMD_17_SVI SVI = {.value = 0};
+	AMD_F17H_SVI SVI = {.value = 0};
 
 	Core_AMD_SMN_Read(	SVI,
 				SMU_AMD_F17_60H_SVI(plane0),
@@ -20604,14 +20604,27 @@ static void Call_DFLT(	const unsigned int plane0, const unsigned int plane1,
 	PUBLIC(RO(Core,AT( PUBLIC(RO(Proc))->Service.Core )))->PowerThermal.VID;
 }
 
+static void Call_Raphael(const unsigned int plane0, const unsigned int plane1,
+			const unsigned long long factor)
+{
+	AMD_F19H_SVI SVI = {.value = 0};
+
+	Call_DFLT(plane0, plane1, factor);
+
+	Core_AMD_SMN_Read(SVI,
+	PUBLIC(RO(Core, AT(PUBLIC(RO(Proc))->Service.Core)))->T.PackageID == 0 ?
+			SMU_AMD_F19H_SVI(plane0) : SMU_AMD_F19H_SVI(plane1),
+				PRIVATE(OF(Zen)).Device.DF);
+
+	PUBLIC(RO(Proc))->PowerThermal.VID.SOC = SVI.SVI1;
+}
+
 static void Call_Genoa( const unsigned int plane0, const unsigned int plane1,
 			const unsigned long long factor )
 {
-	AMD_GNA_SVI SVI = {.value = 0};
-	UNUSED(factor);
+	AMD_F19H_SVI SVI = {.value = 0};
 
-	PUBLIC(RO(Proc))->PowerThermal.VID.CPU = \
-	PUBLIC(RO(Core,AT( PUBLIC(RO(Proc))->Service.Core )))->PowerThermal.VID;
+	Call_DFLT(plane0, plane1, factor);
 
 	Core_AMD_SMN_Read(SVI,
 	PUBLIC(RO(Core, AT(PUBLIC(RO(Proc))->Service.Core)))->T.PackageID == 0 ?
@@ -20669,7 +20682,7 @@ static enum hrtimer_restart Cycle_AMD_Zen3Plus_RMB(struct hrtimer *pTimer)
 }
 static enum hrtimer_restart Cycle_AMD_Zen4_RPL(struct hrtimer *pTimer)
 {
-	return Entry_AMD_F17h(pTimer, Call_MSR_ACCU, Call_DFLT, 0, 0, 0LLU);
+	return Entry_AMD_F17h(pTimer, Call_MSR_ACCU, Call_Raphael, 1, 2, 0LLU);
 }
 static enum hrtimer_restart Cycle_AMD_Zen4_Genoa(struct hrtimer *pTimer)
 {