CVC-RV Errors on TinyTapeout GF 0.2

[d-m-bailey]

Setup

• PDK: gf180mcuD 486fb8633c3d95ae475a5ccd68d0066c25919bb5 (2025.11.22)
• magic: 8.3.538.581
• cvc_rv: 1.1.6
• GDS data: https://github.com/TinyTapeout/tinytapeout-gf-0p2/releases/download/tapeout-ws2512/GDS.zip
• Extraction settings: (set in lvs_config files used in the scripts here.)

EXTRACT_FLATGLOB: 
 *diode_pd2nw_06v0_*[A-Z]*
 *diode_nd2ps_06v0_*[A-Z]*
 *nmos_*_*[A-Z]*
 *mim_*_*[A-Z]*
 *ppolyf_u_*[A-Z]*
 *pmos_*_*[A-Z]*
 *PMOS_*
 *NMOS_*
 *GR_NMOS*
 *moscap_*
 *nmos_clamp_*
 *nmos_*metal_stack*
 *pmos_6p0_esd*
 *comp018green*
 *POWER_RAIL_COR*
 *top_route*
 *METAL_RAIL*
 *Bondpad*
 *_BASE*
 *CLAMP_COR*
 *power_via*
 *FILL*
 *_CDNS_*

EXTRACT_ABSTRACT:
 *__fill_*
 *__endcap
 *__filltie
 *fill_cell

• CVC-RV model settings: link
• CVC-RV power settings: (Project 0)

# Project 0=0000000000

vgnd* power 0.0
vdpwr power 5.0

*(gf180mcu_fd_io__in_c)/PAD input min@0.0 max@5.0
*(gf180mcu_fd_io__bi_24t)/PAD input min@0.0 max@5.0

*(tt_mux)/um_iw[*] expectSim@0.0
*(tt_mux)/um_ena[*] expectSim@0.0
*(tt_mux)/um_pg_ena[*] expectSim@0.0
*(tt_mux)/spine_ow[*] expectSim@0.0

pad_raw[0] input sim@5.0
pad_raw[2] input sim@5.0

/Xtop_I.ctrl_I/Xsel_cnt_gen\[0\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[1\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[2\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[3\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[4\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[5\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[6\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[7\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[8\].cnt_bit_I.cell0_I/Q sim@5*0
/Xtop_I.ctrl_I/Xsel_cnt_gen\[9\].cnt_bit_I.cell0_I/Q sim@5*0

[d-m-bailey]

1. Symptom

The inputs to buffer _1102_ and inverters _0420_ and _0462_ in tt_um_zacky1972_PVTMonitorSuite are never low.

From the cvc.error.gz file:

! Checking nmos gate vs source errors:
 
/Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I(tt_um_zacky1972_PVTMonitorSuite)/X_1102_(PS_gf180mcu_fd_sc_mcu7t5v0__buf_1)/MX3 M nfet_05v0 ad=0.2344p pd=1.56u as=0.1584p ps=1.6u w=0.36u l=0.6u (r=11667)
G: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I
 Min: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I=4600 r=309700
 Sim: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I
 Max: vdpwr@5000 r=3097
S: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/X_1102_/a_36_160#
 Min: vgnd_uq0@0 r=11667
 Sim: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/X_1102_/a_36_160#
 Max: vdpwr@5000 r=6195
D: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0
B: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0

/Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I(tt_um_zacky1972_PVTMonitorSuite)/X_0462_(PS_gf180mcu_fd_sc_mcu7t5v0__clkinv_1)/MX0 M nfet_05v0 ad=0.2112p pd=1.84u as=0.2112p ps=1.84u w=0.48u l=0.6u (r=8750)
G: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I
 Min: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I=4600 r=309700
 Sim: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I
 Max: vdpwr@5000 r=3097
S: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0
D: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_0462_/ZN
 Min: vgnd_uq0@0 r=8750
 Sim: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_0462_/ZN
 Max: vdpwr@5000 r=2869
B: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0

/Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I(tt_um_zacky1972_PVTMonitorSuite)/X_0420_(PS_gf180mcu_fd_sc_mcu7t5v0__clkinv_1)/MX0 M nfet_05v0 ad=0.2112p pd=1.84u as=0.2112p ps=1.84u w=0.48u l=0.6u (r=8750)
G: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I
 Min: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I=4600 r=309700
 Sim: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_1102_/I
 Max: vdpwr@5000 r=3097
S: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0
D: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_0463_/A2
 Min: vgnd_uq0@0 r=8750
 Sim: /Xtop_I.branch\[17\].check_mask.block\[7\].um_I.block_17_7.tt_um_I/_0463_/A2
 Max: vdpwr@5000 r=2869
B: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0

Root Cause

The output of the _0461_ nand gate is connected to one of its inputs. Since the output of a nand gate is only low when both of the inputs are high, the output will never be low. The same input and output net can not be low and high at the same time.

How CVC-RV Detects This

CVC-RV calculates the minimum and maximum voltages for each node. If the gate of a pmos is connected to the drain of the same pmos, then the minimum voltage at the gate/drain is calculated as Vs + Vthp (where Vthp is negative). This is because for any voltage lower than that, the pmos would be on and Vd would equal Vs.

Next Steps

Verify that the gate-level verilog simulation matches the rtl simulation.
The logic synthesizer may have optimized away some logic. Check the original rtl.

[d-m-bailey]

2. Symptom

The inputs to clkinv_1 inverters _210_ and _215_ of tt_um_htfab_cells are logically floating.

From the cvc.error.gz file:

! Checking mos floating input errors:

/Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I(tt_um_htfab_cells)/X_210_(WD_gf180mcu_fd_sc_mcu7t5v0__clkinv_1)/MX1 M pfet_05v0 ad=0.5368p pd=3.32u as=0.5368p ps=3.32u w=1.22u l=0.5u (r=2869)
G: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_210_/I
 Min: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_210_/I
 Sim: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_210_/I
 Max: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_210_/I
S: vdpwr
 Min: vdpwr@5000 r=0
 Sim: vdpwr@5000 r=0
 Max: vdpwr@5000 r=0
D: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_294_/A2
 Min: vgnd_uq0@0 r=8750
 Sim: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_294_/A2
 Max: vdpwr@5000 r=2869
B: vdpwr
 Min: vdpwr@5000 r=0
 Sim: vdpwr@5000 r=0
 Max: vdpwr@5000 r=0

/Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I(tt_um_htfab_cells)/X_210_(WD_gf180mcu_fd_sc_mcu7t5v0__clkinv_1)/MX0 M nfet_05v0 ad=0.2112p pd=1.84u as=0.2112p ps=1.84u w=0.48u l=0.6u (r=8750)
G: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_210_/I
 Min: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_210_/I
 Sim: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_210_/I
 Max: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_210_/I
S: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0
D: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_294_/A2
 Min: vgnd_uq0@0 r=8750
 Sim: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_294_/A2
 Max: vdpwr@5000 r=2869
B: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0

/Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I(tt_um_htfab_cells)/X_215_(WD_gf180mcu_fd_sc_mcu7t5v0__clkinv_1)/MX1 M pfet_05v0 ad=0.5368p pd=3.32u as=0.5368p ps=3.32u w=1.22u l=0.5u (r=2869)
G: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_215_/I
 Min: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_215_/I
 Sim: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_215_/I
 Max: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_215_/I
S: vdpwr
 Min: vdpwr@5000 r=0
 Sim: vdpwr@5000 r=0
 Max: vdpwr@5000 r=0
D: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_314_/A2
 Min: vgnd_uq0@0 r=8750
 Sim: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_314_/A2
 Max: vdpwr@5000 r=2869
B: vdpwr
 Min: vdpwr@5000 r=0
 Sim: vdpwr@5000 r=0
 Max: vdpwr@5000 r=0

/Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I(tt_um_htfab_cells)/X_215_(WD_gf180mcu_fd_sc_mcu7t5v0__clkinv_1)/MX0 M nfet_05v0 ad=0.2112p pd=1.84u as=0.2112p ps=1.84u w=0.48u l=0.6u (r=8750)
G: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_215_/I
 Min: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_215_/I
 Sim: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_215_/I
 Max: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_215_/I
S: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0
D: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_314_/A2
 Min: vgnd_uq0@0 r=8750
 Sim: /Xtop_I.branch\[18\].check_mask.block\[7\].um_I.block_18_7.tt_um_I/_314_/A2
 Max: vdpwr@5000 r=2869
B: vgnd_uq0
 Min: vgnd_uq0@0 r=0
 Sim: vgnd_uq0@0 r=0
 Max: vgnd_uq0@0 r=0

Root Cause

When ena of tt_um_htfab_cells is low, the EN signals of the tri-state buffers in the following diagram are low which results in a Hi-Z input to the inverters.

How CVC-RV Detects This

CVC-RV uses known voltages to propagate logic and ignores devices that are logically off. It then does a second minimum/maximum voltage propagation through the remaining devices. If a gate is missing a minimum and/or maximum voltage, the minimum and maximum source/drain voltages are checked for the possibility of a current leak. If a current leak is possible, CVC-RV flags a floating error.

Next Steps

If the output of the tristate buffers is truly a valid Hi-Z signal, ensure that it is not buffered during synthesis. Otherwise, add logic to ensure a valid level when ena is low.