Sky130 MPW-2

[d-m-bailey]

Key

Grade	Meaning
A	No problems detected
B	Could not run LVS due to missing schematic but no extraction/ERC errors
C	Non-fatal (probably) errors
D	ERC errors
E	LVS errors but maybe partially functional
F	Fatal errors

Summary

Slot	Type	SRAM	Ext	Soft	LVS	CVC	Ext	Soft	LVS	CVC	Grade
A1-001	D		0:11:13	0:00:48	0:02:46	0:00:08	OK	OK	OK	OK	A
A2-002	D		0:16:29	0:01:22	1:21:40	0:00:08	OK	OK	OK	OK	A
A3-003	A		0:00:03	0:00:00	-	0:00:00	OK	OK	NG	?	B
A4-004	D		0:04:53	0:00:24	-	0:00:04	OK	OK	NG	OK	B
A5-005	D		0:43:54	0:03:28	-	0:00:39	OK	OK	NG	NG	D
A6-006	A		0:00:03	0:00:00	-	0:00:00	OK	OK	NG	?	B
B1-007	D		0:24:45	0:01:02	0:39:27	0:00:14	OK	OK	NG	OK	C
B2-008	D	O	1:00:34	0:01:39	11:49:09	0:00:21	OK	OK	OK	OK	A
B3-009	D	O	12:35:36		-	-	NG	NG	NG	-	E
B4-010	D		0:04:36	0:00:16	0:01:10	0:00:02	OK	OK	OK	OK	A
B5-011	A		0:00:07	0:00:00	-	0:00:00	OK	OK	NG	NG	F
B6-012	D	O	0:47:19	0:02:53	-	0:00:35	OK	NG	NG	NG	F
B7-013	A		0:01:27	0:00:12	-	0:00:01	OK	OK	NG	OK	B
C1-014	A		0:00:04	0:00:00	-	0:00:00	OK	NG	NG	OK	B
C2-015	D		0:04:26	0:00:14	0:00:54	0:00:02	OK	OK	OK	OK	A
C3-016	D		0:01:53	0:00:04	0:00:10	0:00:01	OK	OK	OK	OK	A
C4-017	D		0:00:49	0:00:01	0:00:05	0:00:00	OK	OK	NG	NG	F
C6-018	D		0:40:11	0:09:01	0:05:10	0:00:43	OK	OK	NG	NG	D
C7-019	D		0:43:22	0:10:40	11:34:10	0:00:24	OK	OK	NG	OK	A
D1-020	D		0:05:22	0:00:31	0:30:44	0:00:05	OK	OK	NG	OK	B
D2-021	D		0:40:45	0:00:23	11:34:30	0:00:05	OK	OK	NG	NG	D
D3-022	D		0:01:49	0:00:04	0:00:10	0:00:01	OK	OK	OK	OK	A
D4-023	D		0:00:23	0:00:00	-	0:00:00	OK	OK	NG	NG	F
D5-024	D		0:07:35	0:00:28	0:00:19	0:00:07	OK	OK	NG	OK	B
D6-025	D		2:27:56		-	-	NG	NG	NG	-	F
D7-026	A		0:00:14	0:00:00	-	-	OK	NG	NG	-	B
E1-027	D		0:23:31	0:01:41	0:05:44	0:00:16	OK	OK	OK	OK	A
E2-028	D		0:04:21	0:00:10	0:00:39	0:00:03	OK	OK	OK	OK	A
E3-029	A		0:00:19	0:00:00	0:00:03	0:00:00	OK	OK	NG	OK	E
E4-030	D		0:00:23	0:00:00	0:03:01	0:00:00	OK	OK	NG	OK	B
E5-031	D		0:08:51	0:00:23	0:01:12	0:00:23	OK	OK	OK	OK	A
E6-032	D		0:00:52	0:00:00	0:00:04	0:00:00	OK	OK	OK	NG	C
E7-033	A		0:01:07	0:00:05	-	0:00:00	OK	OK	NG	OK	B
F1-034	D		0:07:18	0:00:29	0:00:19	0:00:08	OK	OK	NG	OK	B
F2-035	D		0:03:35	0:00:17	0:10:34	0:00:02	OK	OK	NG	OK	B
F3-036	D		0:45:40	1:22:58	0:04:47	0:00:46	OK	OK	OK	OK	A
F4-037	A		0:00:05	0:00:00	-	-	OK	NG	NG	-	D
F5-038	A		0:00:03	0:00:01	0:00:01	0:00:00	OK	OK	NG	OK	C
F6-039	D		0:04:52	0:00:21	0:01:32	0:00:06	OK	OK	OK	NG	C
F7-040	A	O	3:13:46	0:26:53	-	-	OK	NG	NG	-	F

Link to the manifest

[d-m-bailey]

Slot A3-003:
LVS: missing source netlist.
CVC: Design uses vdda1 which must be limited to 1.8V because thin-ox devices are used. With vdda1 set to 1.8V, there are no CVC errors.

[d-m-bailey]

Slot A4-004:
LVS: missing source netlist.

[d-m-bailey]

Slot A5-005:
LVS: missing source netlist.
CVC: 7 inputs are not connected.

/Xinst_eFPGA_top/sky130_fd_sc_hd__clkdlybuf4s50_1_6/A
/Xinst_eFPGA_top/sky130_fd_sc_hd__clkdlybuf4s50_1_8/A
/Xinst_eFPGA_top/sky130_fd_sc_hd__clkdlybuf4s50_1_9/A
/Xinst_eFPGA_top/sky130_fd_sc_hd__clkdlybuf4s50_1_11/A
/Xinst_eFPGA_top/sky130_fd_sc_hd__dlygate4sd3_1_227/A
/Xinst_eFPGA_top/sky130_fd_sc_hd__dlygate4sd3_1_499/A
/Xinst_eFPGA_top/sky130_fd_sc_hd__dlygate4sd3_1_556/A

[d-m-bailey]

Slot A6-006:
LVS: missing source netlist.
CVC: Design uses vdda1 which must be limited to 1.8V because thin-ox devices are used. With vdda1 set to 1.8V, there are no CVC errors.

[d-m-bailey]

Slot B1-007:
LVS: buffering discrepancy. May lead to timing problem.

[dineshannayya]

Can you give more details on failures and which MACRO OR SOC buffering are impacted.

[d-m-bailey]

@dineshannayya Here's the top level correspondence. Is this enough information?

Layout                                                    |Netlist
----------------------------------------------------------|----------------------------------------------------------
*scr1_top_wb:u_riscv_top/_27207_/X **not pin**            |la_data_out[0]
*scr1_top_wb:u_riscv_top/_27248_/Y **not pin**            |la_data_out[8]
*scr1_top_wb:u_riscv_top/_35655_/Y **not pin**            |la_data_out[52]
*spim_top:u_spi_master/_13477_/Q **not pin**              |la_data_out[83]
la_data_out[0]                                            |*u_riscv_top/psn_net_450 **not a pin** 
la_data_out[8]                                            |*u_riscv_top/psn_net_542 **not a pin** 
la_data_out[52]                                           |*u_riscv_top/psn_net_2906 **not a pin** 
la_data_out[83]                                           |*u_spi_master/psn_net_148 **not a pin**

[dineshannayya]

@d-m-bailey Thanks for details. All the 4 pins are debug monitoring signal, will not have functional impact. I will try to cross-check these bit silicon behavior against simulation.

What is this error actually indicates - not pin

Here are my observation on netlist connectivity.

Failing Node :
1. la_data_out[0] : pin is going out from 27207/Y and also feed back to psn_inst_psn_buff_450/A.
2. la_data_out[8] : pin is going out from 27248/Y and also feed back to psn_inst_psn_buff_542/A.
3. la_data_out[52] : pin is going out from 35655/Y and also feed back to psn_net_2906/A.
4. la_data_out[83] : pin is going out from 13477/Y and also feed back to psn_net_148/A.

Non Failing Node:
1. la_data_out[1] : Non failing debug signal la_data_out[1] -> This port does not has any feed back.

Looks to me LVS tool having issue, when the output port signal has a feedback path ?

Debug connectivity of riscv_debug[0] => la_data_out[0]

sky130_fd_sc_hd__buf_2 27207 (.A(22423),
.X(riscv_debug[0]),
.VGND(vssd1),
.VNB(vssd1),
.VPB(vccd1),
.VPWR(vccd1));

sky130_fd_sc_hd__buf_8 psn_inst_psn_buff_450 (.A(riscv_debug[0]),
.X(psn_net_450),
.VGND(vssd1),
.VNB(vssd1),
.VPB(vccd1),
.VPWR(vccd1));

Debug connectivity of riscv_debug[8] => la_data_out[8]

sky130_fd_sc_hd__buf_8 psn_inst_psn_buff_542 (.A(riscv_debug[8]),
.X(psn_net_542),
.VGND(vssd1),
.VNB(vssd1),
.VPB(vccd1),
.VPWR(vccd1));

sky130_fd_sc_hd__nor2_4 27248 (.A(psn_net_449),
.B(22403),
.Y(riscv_debug[8]),
.VGND(vssd1),
.VNB(vssd1),
.VPB(vccd1),
.VPWR(vccd1));

Debug connectivity of riscv_debug[52] => la_data_out[52]

sky130_fd_sc_hd__nor2_4 35655 (.A(04242),
.B(04509),
.Y(riscv_debug[52]),
.VGND(vssd1),
.VNB(vssd1),
.VPB(vccd1),
.VPWR(vccd1));

Debug connectivity of la_data_out[83]

 sky130_fd_sc_hd__dfrtp_4 _13477_ (.D(_00894_),
.Q(spi_debug[19]),
.RESET_B(rst_n),
.CLK(clknet_7_31_0_mclk),
.VGND(vssd1),
.VNB(vssd1),
.VPB(vccd1),
.VPWR(vccd1));

sky130_fd_sc_hd__buf_2 psn_inst_psn_buff_148 (.A(spi_debug[19]),
.X(psn_net_148),
.VGND(vssd1),
.VNB(vssd1),
.VPB(vccd1),
.VPWR(vccd1));

[d-m-bailey]

What is this error actually indicates - not pin

This is an enhancement that I added to netgen. Previously, the report would have been something like

Layout                                                    |Netlist
----------------------------------------------------------|----------------------------------------------------------
*no match*                                                |la_data_out[0]
*no match*                                                |la_data_out[8]
*no match*                                                |la_data_out[52]
*no match*                                                |la_data_out[83]
la_data_out[0]                                            |*no match* 
la_data_out[8]                                            |*no match* 
la_data_out[52]                                           |*no match*
la_data_out[83]                                           |*no match*

With the change you can see what net the pins match in the other netlist.

Looks to me LVS tool having issue, when the output port signal has a feedback path ?

From what I could tell, the netlists match topologically and the pins have the correct logic, but the location of the pins on the buffer chains is different between the layout and verilog. To me it seems like a synthesis or buffer insertion problem.

[d-m-bailey]

Slot B3-009:
Extract: Short in 1rw memories.

[mguthaus]

This slot was replaced with MPW3 slot-015

[mguthaus]

And it was fixed there:

[d-m-bailey]

@mguthaus Great! Since the mpw-2 chips are out, I'm just (re)posting the back end verification results here to hopefully aid in debugging.

[d-m-bailey]

@mguthaus I noticed that you added a note on the OpenMPW silicon bringup data sheet that the verification was of the wrong data. The gds that I'm using is from https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-two/slot-009
Is that the wrong data?

Actually, the screen shot that I posted was from last year's verification, but I see the same error in the current mpw-2 gds. I'm trying to re-extract with magic, but the job has been running for over a week.

[mguthaus]

Yes, they supposedly substituted my MPW3 design which had a density fix in the largest macro. Rather than also fix the previous MPW2 design with several known issues (hold time problems due to the same issue on MPW1 as well as the one you pointed out), they just substituted the design.

[d-m-bailey]

Slot B5-011
LVS: missing source netlist.
CVC: Forward bias pfet drain-bulk junction

Missing mcon

[d-m-bailey]

Slot B6-012
Extract: vssd1 - vccd1 met4 short

CVC: 5 nwell missing connections to vccd1 in eFPGA_CPU_top

[d-m-bailey]

Slot B7-013
Extract: text from multiple hierarchies flattened resulting in many shorts. (used hierarchical design instead but not equal to tapeout data).
LVS: missing source netlist.

[d-m-bailey]

Slot C1-014
Extract: inductor not extracted.
LVS: missing source netlist.

[d-m-bailey]

Slot C4-017
Extract: layout cells have conflicting text.

LVS/CVC: There is a routing power short. The wire that shorts to ground is connect to a tie high conb cell.

[thesourcerer8]

Thanks, as far as I remember, I had discovered those issues a few days after the submission deadline. I then submitted a corrected version at mpw3.

[d-m-bailey]

@thesourcerer8 Great! Interested in the results.

[d-m-bailey]

C6-018
LVS: missing powered sub module verilog
CVC: unconnected logic inputs

/Xmprj/sky130_fd_sc_hd__a221o_1_519/B2
/Xmprj/sky130_fd_sc_hd__a221o_1_525/B2
/Xmprj/sky130_fd_sc_hd__a221o_1_580/B2
/Xmprj/sky130_fd_sc_hd__a221o_1_600/B2
/Xmprj/sky130_fd_sc_hd__a221o_1_603/B2
/Xmprj/sky130_fd_sc_hd__a221o_1_604/B2
/Xmprj/sky130_fd_sc_hd__a221o_1_605/B2
/Xmprj/sky130_fd_sc_hd__a221o_1_647/B2
/Xmprj/sky130_fd_sc_hd__a222oi_1_757/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_757/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_758/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_758/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_759/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_759/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_760/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_760/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_761/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_761/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_762/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_762/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_763/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_763/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_764/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_764/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_765/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_765/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_786/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_786/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_787/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_787/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_788/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_788/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_789/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_789/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_790/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_790/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_791/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_791/B1
/Xmprj/sky130_fd_sc_hd__a222oi_1_792/A1
/Xmprj/sky130_fd_sc_hd__a222oi_1_792/B1

[d-m-bailey]

C7-019
LVS: ignore decap cells (need to equate layout sky130_ef_sc_hd__decap_12 to netlist sky130_fd_sc_hd__decap_12)

[d-m-bailey]

D1-020
LVS: Different number & type of cells

Flattening unmatched subcell sky130_fd_sc_hd__o2bb2ai_2 in circuit user_proj_example (1)(3 instances)
Flattening unmatched subcell sky130_fd_sc_hd__o2bb2a_4 in circuit user_proj_example (1)(1 instance)
Flattening unmatched subcell sky130_fd_sc_hd__nand2b_2 in circuit user_proj_example (1)(1 instance)
Flattening unmatched subcell sky130_fd_sc_hd__a41o_4 in circuit user_proj_example (1)(1 instance)
Flattening unmatched subcell sky130_fd_sc_hd__nand3_1 in circuit user_proj_example (1)(1 instance)
Flattening unmatched subcell sky130_fd_sc_hd__nor2b_2 in circuit user_proj_example (1)(1 instance)
Flattening unmatched subcell sky130_fd_sc_hd__nand4_1 in circuit user_proj_example (1)(3 instances)
Flattening unmatched subcell sky130_fd_sc_hd__o2111ai_1 in circuit user_proj_example (1)(1 instance)
Flattening unmatched subcell sky130_fd_sc_hd__dfstp_1 in circuit user_proj_example (1)(1 instance)
...
Number of devices: 43688 **Mismatch**      |Number of devices: 28174 **Mismatch**
Number of nets: 33007 **Mismatch**         |Number of nets: 17575 **Mismatch**

[d-m-bailey]

Slot D2-021
Extract: all vccd* shorted to vdda*. all vssd* shorted to vssa*.
LVS: missing source submodules fpga_top, etc.
CVC: Unconnected gates

[d-m-bailey]

Slot D6-025
Extract: No text on top layout
LVS/SOFT: Can't run LVS or SOFT checks because no pins in top layout
CVC: Unconnected pins from GcdWrapper to user_project_wrapper
example

[d-m-bailey]

Slot D7-026
Extract: Flattened layout has conflicting text from multiple hierarchies. Removing hierarchical text and adding SUBCUT around vssa2 region yields clean extract.
LVS: no source netlist
CVC: probably ok

[d-m-bailey]

Slot E2-028
LVS: fakediode cells extract as empty devices. LVS passes if fakediodes are ignored.

[d-m-bailey]

Slot E3-029
LVS: flatten pll_top_v1, pll_top_v2, test_gate.
io_analog[0] and io_analog[1] are reversed in the layout. (see screen shot)
CVC: thin-ox devices are used with vdda1. vdda1 should be limited to 1.8V

[d-m-bailey]

Slot E4-030
LVS: No source netlist
Soft: unconnected substrate/well taps

[d-m-bailey]

Slot E5-031
LVS: extra ports for unused power (not a problem)

[d-m-bailey]

Slot E6-032
CVC: user_project_wrapper port user_clock2 is not connected to the user_proj_example port user_clock2. This results in an open input to the buffer input295. The output of the buffer is not used anywhere, so the overall effect should be minimal.

[d-m-bailey]

Slot E7-033
Extract: Added SUBCUT for LDO and dpll
LVS: missing analog source netlist

[d-m-bailey]

Slot F1-034
LVS: missing gate level powered verilog for these macros.

fbless_graphics_core
wrapped_a51
wrapped_bfloat16
wrapped_chacha_wb_accel
wrapped_frequency_counter
wrapped_gfxdemo
wrapped_hack_soc
wrapped_hoggephase_project
wrapped_memLCDdriver
wrapped_newmot
wrapped_pong
wrapped_qarma
wrapped_quad_pwm_fet_drivers
wrapped_rgb_mixer
wrapped_wb_hyperram
wrapper_fibonacci

[d-m-bailey]

Slot F2-035
LVS: source netlist contains different number and type of standard cells:

[d-m-bailey]

Slot F3-036
Extract: user_proj_example layout has no text or pins (flatten before extraction)
LVS: verilog has no decap/fill/tapvpwrvgnd cells
verilog/layout have intentionally shorted ports. extract with ext2spice short resistor.

[d-m-bailey]

Slot F4-037
CVC: Unconnected gates

[d-m-bailey]

Slot F5-038
Extract: Add SUBCUT
LVS: cellA GND net in schematic should be VSS.
resistor size mismatch. schematic L=20u, layout L=7u

[d-m-bailey]

Slot F6-039
CVC: user_project_wrapper port user_clock2 is not connected to the wrapper_fibonacci port user_clock2. This results in an open input to the buffer input104. The output of the buffer is not used anywhere, so the overall effect should be minimal.

[d-m-bailey]

Slot F7-040
Extraction: Looks like there's some unconnected power.