Does it really work?

[sorgelig]

Hi!

I'm trying to port it to MiSTer (Altera Cyclone V) and the only thing i see is RAM CHECK screen with 3 white RAM items and 4th yellow. All lines are -OK-.
There is no further processing.

Does it require specific set of 1942 ROMs?
May be something in the code synthesized differently on Altera. I don't see any meaningful errors while compilation.

[d18c7db]

The script that converts the binary ROMs to VHDL is at FPGA_1942/source/boards/pipistrello/scripts/build_roms_1942.bat Inside that script you can see the crc and sha of each of the rom file required. This way you can check that you have the correct files. Also from memory my implementation with the ROMs I used goes straight into the game demo at power up. It does not show any rom tests. Check that you haven’t accidentally inverted the levels on the game dip switches and you game maybe goes into test mode?

[d18c7db]

Did you make any progress with this?

[sorgelig]

There is other 1942 core made by Jotego which is precise replica: https://github.com/jotego/jt_gng
I've already ported it to MiSTer and will release soon.